1*ff2743e5SAnson Huang /* 2*ff2743e5SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*ff2743e5SAnson Huang * 4*ff2743e5SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*ff2743e5SAnson Huang */ 6*ff2743e5SAnson Huang 7*ff2743e5SAnson Huang #include <mmio.h> 8*ff2743e5SAnson Huang #include "imx8_mu.h" 9*ff2743e5SAnson Huang 10*ff2743e5SAnson Huang void MU_EnableRxFullInt(uint32_t base, uint32_t index) 11*ff2743e5SAnson Huang { 12*ff2743e5SAnson Huang uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 13*ff2743e5SAnson Huang 14*ff2743e5SAnson Huang reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 15*ff2743e5SAnson Huang reg |= MU_CR_RIE0_MASK1 >> index; 16*ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 17*ff2743e5SAnson Huang } 18*ff2743e5SAnson Huang 19*ff2743e5SAnson Huang void MU_EnableGeneralInt(uint32_t base, uint32_t index) 20*ff2743e5SAnson Huang { 21*ff2743e5SAnson Huang uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 22*ff2743e5SAnson Huang 23*ff2743e5SAnson Huang reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 24*ff2743e5SAnson Huang reg |= MU_CR_GIE0_MASK1 >> index; 25*ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 26*ff2743e5SAnson Huang } 27*ff2743e5SAnson Huang 28*ff2743e5SAnson Huang void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg) 29*ff2743e5SAnson Huang { 30*ff2743e5SAnson Huang uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; 31*ff2743e5SAnson Huang 32*ff2743e5SAnson Huang /* Wait TX register to be empty. */ 33*ff2743e5SAnson Huang while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 34*ff2743e5SAnson Huang ; 35*ff2743e5SAnson Huang mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg); 36*ff2743e5SAnson Huang } 37*ff2743e5SAnson Huang 38*ff2743e5SAnson Huang void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg) 39*ff2743e5SAnson Huang { 40*ff2743e5SAnson Huang uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; 41*ff2743e5SAnson Huang 42*ff2743e5SAnson Huang /* Wait RX register to be full. */ 43*ff2743e5SAnson Huang while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 44*ff2743e5SAnson Huang ; 45*ff2743e5SAnson Huang *msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4)); 46*ff2743e5SAnson Huang } 47*ff2743e5SAnson Huang 48*ff2743e5SAnson Huang void MU_Init(uint32_t base) 49*ff2743e5SAnson Huang { 50*ff2743e5SAnson Huang uint32_t reg; 51*ff2743e5SAnson Huang 52*ff2743e5SAnson Huang reg = mmio_read_32(base + MU_ACR_OFFSET1); 53*ff2743e5SAnson Huang /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 54*ff2743e5SAnson Huang reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 55*ff2743e5SAnson Huang | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 56*ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 57*ff2743e5SAnson Huang } 58