1ff2743e5SAnson Huang /* 2ff2743e5SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3ff2743e5SAnson Huang * 4ff2743e5SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5ff2743e5SAnson Huang */ 6ff2743e5SAnson Huang 709d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 809d40e0eSAntonio Nino Diaz 9ff2743e5SAnson Huang #include "imx8_mu.h" 10ff2743e5SAnson Huang 11*3a2b5199SAnson Huang void MU_Resume(uint32_t base) 12*3a2b5199SAnson Huang { 13*3a2b5199SAnson Huang uint32_t reg, i; 14*3a2b5199SAnson Huang 15*3a2b5199SAnson Huang reg = mmio_read_32(base + MU_ACR_OFFSET1); 16*3a2b5199SAnson Huang /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 17*3a2b5199SAnson Huang reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 18*3a2b5199SAnson Huang | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 19*3a2b5199SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 20*3a2b5199SAnson Huang 21*3a2b5199SAnson Huang /* Enable all RX interrupts */ 22*3a2b5199SAnson Huang for (i = 0; i < MU_RR_COUNT; i++) 23*3a2b5199SAnson Huang MU_EnableRxFullInt(base, i); 24*3a2b5199SAnson Huang } 25*3a2b5199SAnson Huang 26ff2743e5SAnson Huang void MU_EnableRxFullInt(uint32_t base, uint32_t index) 27ff2743e5SAnson Huang { 28ff2743e5SAnson Huang uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 29ff2743e5SAnson Huang 30ff2743e5SAnson Huang reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 31ff2743e5SAnson Huang reg |= MU_CR_RIE0_MASK1 >> index; 32ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 33ff2743e5SAnson Huang } 34ff2743e5SAnson Huang 35ff2743e5SAnson Huang void MU_EnableGeneralInt(uint32_t base, uint32_t index) 36ff2743e5SAnson Huang { 37ff2743e5SAnson Huang uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 38ff2743e5SAnson Huang 39ff2743e5SAnson Huang reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 40ff2743e5SAnson Huang reg |= MU_CR_GIE0_MASK1 >> index; 41ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 42ff2743e5SAnson Huang } 43ff2743e5SAnson Huang 44ff2743e5SAnson Huang void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg) 45ff2743e5SAnson Huang { 46ff2743e5SAnson Huang uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; 47ff2743e5SAnson Huang 48ff2743e5SAnson Huang /* Wait TX register to be empty. */ 49ff2743e5SAnson Huang while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 50ff2743e5SAnson Huang ; 51ff2743e5SAnson Huang mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg); 52ff2743e5SAnson Huang } 53ff2743e5SAnson Huang 54ff2743e5SAnson Huang void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg) 55ff2743e5SAnson Huang { 56ff2743e5SAnson Huang uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; 57ff2743e5SAnson Huang 58ff2743e5SAnson Huang /* Wait RX register to be full. */ 59ff2743e5SAnson Huang while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 60ff2743e5SAnson Huang ; 61ff2743e5SAnson Huang *msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4)); 62ff2743e5SAnson Huang } 63ff2743e5SAnson Huang 64ff2743e5SAnson Huang void MU_Init(uint32_t base) 65ff2743e5SAnson Huang { 66ff2743e5SAnson Huang uint32_t reg; 67ff2743e5SAnson Huang 68ff2743e5SAnson Huang reg = mmio_read_32(base + MU_ACR_OFFSET1); 69ff2743e5SAnson Huang /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 70ff2743e5SAnson Huang reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 71ff2743e5SAnson Huang | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 72ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 73ff2743e5SAnson Huang } 74