1ff2743e5SAnson Huang /* 2ff2743e5SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3ff2743e5SAnson Huang * 4ff2743e5SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5ff2743e5SAnson Huang */ 6ff2743e5SAnson Huang 7*09d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 8*09d40e0eSAntonio Nino Diaz 9ff2743e5SAnson Huang #include "imx8_mu.h" 10ff2743e5SAnson Huang 11ff2743e5SAnson Huang void MU_EnableRxFullInt(uint32_t base, uint32_t index) 12ff2743e5SAnson Huang { 13ff2743e5SAnson Huang uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 14ff2743e5SAnson Huang 15ff2743e5SAnson Huang reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 16ff2743e5SAnson Huang reg |= MU_CR_RIE0_MASK1 >> index; 17ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 18ff2743e5SAnson Huang } 19ff2743e5SAnson Huang 20ff2743e5SAnson Huang void MU_EnableGeneralInt(uint32_t base, uint32_t index) 21ff2743e5SAnson Huang { 22ff2743e5SAnson Huang uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); 23ff2743e5SAnson Huang 24ff2743e5SAnson Huang reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); 25ff2743e5SAnson Huang reg |= MU_CR_GIE0_MASK1 >> index; 26ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 27ff2743e5SAnson Huang } 28ff2743e5SAnson Huang 29ff2743e5SAnson Huang void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg) 30ff2743e5SAnson Huang { 31ff2743e5SAnson Huang uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; 32ff2743e5SAnson Huang 33ff2743e5SAnson Huang /* Wait TX register to be empty. */ 34ff2743e5SAnson Huang while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 35ff2743e5SAnson Huang ; 36ff2743e5SAnson Huang mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg); 37ff2743e5SAnson Huang } 38ff2743e5SAnson Huang 39ff2743e5SAnson Huang void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg) 40ff2743e5SAnson Huang { 41ff2743e5SAnson Huang uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; 42ff2743e5SAnson Huang 43ff2743e5SAnson Huang /* Wait RX register to be full. */ 44ff2743e5SAnson Huang while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) 45ff2743e5SAnson Huang ; 46ff2743e5SAnson Huang *msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4)); 47ff2743e5SAnson Huang } 48ff2743e5SAnson Huang 49ff2743e5SAnson Huang void MU_Init(uint32_t base) 50ff2743e5SAnson Huang { 51ff2743e5SAnson Huang uint32_t reg; 52ff2743e5SAnson Huang 53ff2743e5SAnson Huang reg = mmio_read_32(base + MU_ACR_OFFSET1); 54ff2743e5SAnson Huang /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ 55ff2743e5SAnson Huang reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 56ff2743e5SAnson Huang | MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1); 57ff2743e5SAnson Huang mmio_write_32(base + MU_ACR_OFFSET1, reg); 58ff2743e5SAnson Huang } 59