1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <common/bl_common.h> 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gicv3.h> 12 #include <drivers/arm/arm_gicv3_common.h> 13 #include <lib/mmio.h> 14 #include <lib/utils.h> 15 #include <plat/common/platform.h> 16 17 #include <plat_imx8.h> 18 19 /* the GICv3 driver only needs to be initialized in EL3 */ 20 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 21 22 static const interrupt_prop_t g01s_interrupt_props[] = { 23 INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY, 24 INTR_GROUP1S, GIC_INTR_CFG_LEVEL), 25 INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY, 26 INTR_GROUP0, GIC_INTR_CFG_LEVEL), 27 }; 28 29 static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr) 30 { 31 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 32 } 33 34 const gicv3_driver_data_t arm_gic_data = { 35 .gicd_base = PLAT_GICD_BASE, 36 .gicr_base = PLAT_GICR_BASE, 37 .interrupt_props = g01s_interrupt_props, 38 .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props), 39 .rdistif_num = PLATFORM_CORE_COUNT, 40 .rdistif_base_addrs = rdistif_base_addrs, 41 .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos, 42 }; 43 44 void plat_gic_driver_init(void) 45 { 46 /* 47 * the GICv3 driver is initialized in EL3 and does not need 48 * to be initialized again in S-EL1. This is because the S-EL1 49 * can use GIC system registers to manage interrupts and does 50 * not need GIC interface base addresses to be configured. 51 */ 52 #if IMAGE_BL31 53 gicv3_driver_init(&arm_gic_data); 54 #endif 55 } 56 57 static __inline void plat_gicr_exit_sleep(void) 58 { 59 unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER); 60 61 /* 62 * ProcessorSleep bit can ONLY be set to zero when 63 * Quiescent bit and Sleep bit are both zero, so 64 * need to make sure Quiescent bit and Sleep bit 65 * are zero before clearing ProcessorSleep bit. 66 */ 67 if (val & WAKER_QSC_BIT) { 68 mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT); 69 /* Wait till the WAKER_QSC_BIT changes to 0 */ 70 while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U) 71 ; 72 } 73 } 74 75 void plat_gic_init(void) 76 { 77 plat_gicr_exit_sleep(); 78 gicv3_distif_init(); 79 gicv3_rdistif_init(plat_my_core_pos()); 80 gicv3_cpuif_enable(plat_my_core_pos()); 81 } 82 83 void plat_gic_cpuif_enable(void) 84 { 85 gicv3_cpuif_enable(plat_my_core_pos()); 86 } 87 88 void plat_gic_cpuif_disable(void) 89 { 90 gicv3_cpuif_disable(plat_my_core_pos()); 91 } 92 93 void plat_gic_pcpu_init(void) 94 { 95 gicv3_rdistif_init(plat_my_core_pos()); 96 } 97 98 void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx) 99 { 100 /* save the gic rdist/dist context */ 101 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) 102 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); 103 gicv3_distif_save(&ctx->dist_ctx); 104 } 105 106 void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx) 107 { 108 /* restore the gic rdist/dist context */ 109 gicv3_distif_init_restore(&ctx->dist_ctx); 110 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) 111 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); 112 } 113