1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <common/bl_common.h> 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gicv3.h> 12 #include <drivers/arm/arm_gicv3_common.h> 13 #include <lib/mmio.h> 14 #include <lib/utils.h> 15 #include <plat/common/platform.h> 16 17 #include <plat_imx8.h> 18 19 /* the GICv3 driver only needs to be initialized in EL3 */ 20 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 21 22 static const interrupt_prop_t g01s_interrupt_props[] = { 23 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, 24 INTR_GROUP0, GIC_INTR_CFG_LEVEL), 25 }; 26 27 static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr) 28 { 29 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 30 } 31 32 const gicv3_driver_data_t arm_gic_data = { 33 .gicd_base = PLAT_GICD_BASE, 34 .gicr_base = PLAT_GICR_BASE, 35 .interrupt_props = g01s_interrupt_props, 36 .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props), 37 .rdistif_num = PLATFORM_CORE_COUNT, 38 .rdistif_base_addrs = rdistif_base_addrs, 39 .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos, 40 }; 41 42 void plat_gic_driver_init(void) 43 { 44 /* 45 * the GICv3 driver is initialized in EL3 and does not need 46 * to be initialized again in S-EL1. This is because the S-EL1 47 * can use GIC system registers to manage interrupts and does 48 * not need GIC interface base addresses to be configured. 49 */ 50 #if IMAGE_BL31 51 gicv3_driver_init(&arm_gic_data); 52 #endif 53 } 54 55 static __inline void plat_gicr_exit_sleep(void) 56 { 57 unsigned int val = mmio_read_32(PLAT_GICR_BASE + GICR_WAKER); 58 59 /* 60 * ProcessorSleep bit can ONLY be set to zero when 61 * Quiescent bit and Sleep bit are both zero, so 62 * need to make sure Quiescent bit and Sleep bit 63 * are zero before clearing ProcessorSleep bit. 64 */ 65 if (val & WAKER_QSC_BIT) { 66 mmio_write_32(PLAT_GICR_BASE + GICR_WAKER, val & ~WAKER_SL_BIT); 67 /* Wait till the WAKER_QSC_BIT changes to 0 */ 68 while ((mmio_read_32(PLAT_GICR_BASE + GICR_WAKER) & WAKER_QSC_BIT) != 0U) 69 ; 70 } 71 } 72 73 void plat_gic_init(void) 74 { 75 plat_gicr_exit_sleep(); 76 gicv3_distif_init(); 77 gicv3_rdistif_init(plat_my_core_pos()); 78 gicv3_cpuif_enable(plat_my_core_pos()); 79 } 80 81 void plat_gic_cpuif_enable(void) 82 { 83 gicv3_cpuif_enable(plat_my_core_pos()); 84 } 85 86 void plat_gic_cpuif_disable(void) 87 { 88 gicv3_cpuif_disable(plat_my_core_pos()); 89 } 90 91 void plat_gic_pcpu_init(void) 92 { 93 gicv3_rdistif_init(plat_my_core_pos()); 94 } 95 96 void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx) 97 { 98 /* save the gic rdist/dist context */ 99 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) 100 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); 101 gicv3_distif_save(&ctx->dist_ctx); 102 } 103 104 void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx) 105 { 106 /* restore the gic rdist/dist context */ 107 gicv3_distif_init_restore(&ctx->dist_ctx); 108 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) 109 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); 110 } 111