1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <bl_common.h> 8 #include <gicv3.h> 9 #include <interrupt_props.h> 10 #include <plat_imx8.h> 11 #include <platform.h> 12 #include <platform_def.h> 13 #include <utils.h> 14 15 /* the GICv3 driver only needs to be initialized in EL3 */ 16 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 17 18 static const interrupt_prop_t g01s_interrupt_props[] = { 19 INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY, 20 INTR_GROUP1S, GIC_INTR_CFG_LEVEL), 21 INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY, 22 INTR_GROUP0, GIC_INTR_CFG_LEVEL), 23 }; 24 25 static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr) 26 { 27 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 28 } 29 30 const gicv3_driver_data_t arm_gic_data = { 31 .gicd_base = PLAT_GICD_BASE, 32 .gicr_base = PLAT_GICR_BASE, 33 .interrupt_props = g01s_interrupt_props, 34 .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props), 35 .rdistif_num = PLATFORM_CORE_COUNT, 36 .rdistif_base_addrs = rdistif_base_addrs, 37 .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos, 38 }; 39 40 void plat_gic_driver_init(void) 41 { 42 /* 43 * the GICv3 driver is initialized in EL3 and does not need 44 * to be initialized again in S-EL1. This is because the S-EL1 45 * can use GIC system registers to manage interrupts and does 46 * not need GIC interface base addresses to be configured. 47 */ 48 #if IMAGE_BL31 49 gicv3_driver_init(&arm_gic_data); 50 #endif 51 } 52 53 void plat_gic_init(void) 54 { 55 gicv3_distif_init(); 56 gicv3_rdistif_init(plat_my_core_pos()); 57 gicv3_cpuif_enable(plat_my_core_pos()); 58 } 59 60 void plat_gic_cpuif_enable(void) 61 { 62 gicv3_cpuif_enable(plat_my_core_pos()); 63 } 64 65 void plat_gic_cpuif_disable(void) 66 { 67 gicv3_cpuif_disable(plat_my_core_pos()); 68 } 69 70 void plat_gic_pcpu_init(void) 71 { 72 gicv3_rdistif_init(plat_my_core_pos()); 73 } 74