1bd08def3SAnson Huang /* 2bd08def3SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3bd08def3SAnson Huang * 4bd08def3SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5bd08def3SAnson Huang */ 6bd08def3SAnson Huang 7bd08def3SAnson Huang #include <platform_def.h> 809d40e0eSAntonio Nino Diaz 909d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 1009d40e0eSAntonio Nino Diaz #include <common/interrupt_props.h> 1109d40e0eSAntonio Nino Diaz #include <drivers/arm/gicv3.h> 1209d40e0eSAntonio Nino Diaz #include <lib/utils.h> 1309d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 1409d40e0eSAntonio Nino Diaz 1509d40e0eSAntonio Nino Diaz #include <plat_imx8.h> 16bd08def3SAnson Huang 17bd08def3SAnson Huang /* the GICv3 driver only needs to be initialized in EL3 */ 18bd08def3SAnson Huang uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 19bd08def3SAnson Huang 20601d2f3cSAntonio Nino Diaz static const interrupt_prop_t g01s_interrupt_props[] = { 21601d2f3cSAntonio Nino Diaz INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY, 22601d2f3cSAntonio Nino Diaz INTR_GROUP1S, GIC_INTR_CFG_LEVEL), 23601d2f3cSAntonio Nino Diaz INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY, 24601d2f3cSAntonio Nino Diaz INTR_GROUP0, GIC_INTR_CFG_LEVEL), 25601d2f3cSAntonio Nino Diaz }; 26bd08def3SAnson Huang 27bd08def3SAnson Huang static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr) 28bd08def3SAnson Huang { 29bd08def3SAnson Huang return (unsigned int)plat_core_pos_by_mpidr(mpidr); 30bd08def3SAnson Huang } 31bd08def3SAnson Huang 32bd08def3SAnson Huang const gicv3_driver_data_t arm_gic_data = { 33bd08def3SAnson Huang .gicd_base = PLAT_GICD_BASE, 34bd08def3SAnson Huang .gicr_base = PLAT_GICR_BASE, 35601d2f3cSAntonio Nino Diaz .interrupt_props = g01s_interrupt_props, 36601d2f3cSAntonio Nino Diaz .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props), 37bd08def3SAnson Huang .rdistif_num = PLATFORM_CORE_COUNT, 38bd08def3SAnson Huang .rdistif_base_addrs = rdistif_base_addrs, 39bd08def3SAnson Huang .mpidr_to_core_pos = plat_imx_mpidr_to_core_pos, 40bd08def3SAnson Huang }; 41bd08def3SAnson Huang 42bd08def3SAnson Huang void plat_gic_driver_init(void) 43bd08def3SAnson Huang { 44bd08def3SAnson Huang /* 45bd08def3SAnson Huang * the GICv3 driver is initialized in EL3 and does not need 46bd08def3SAnson Huang * to be initialized again in S-EL1. This is because the S-EL1 47bd08def3SAnson Huang * can use GIC system registers to manage interrupts and does 48bd08def3SAnson Huang * not need GIC interface base addresses to be configured. 49bd08def3SAnson Huang */ 50bd08def3SAnson Huang #if IMAGE_BL31 51bd08def3SAnson Huang gicv3_driver_init(&arm_gic_data); 52bd08def3SAnson Huang #endif 53bd08def3SAnson Huang } 54bd08def3SAnson Huang 55bd08def3SAnson Huang void plat_gic_init(void) 56bd08def3SAnson Huang { 57bd08def3SAnson Huang gicv3_distif_init(); 58bd08def3SAnson Huang gicv3_rdistif_init(plat_my_core_pos()); 59bd08def3SAnson Huang gicv3_cpuif_enable(plat_my_core_pos()); 60bd08def3SAnson Huang } 61bd08def3SAnson Huang 62bd08def3SAnson Huang void plat_gic_cpuif_enable(void) 63bd08def3SAnson Huang { 64bd08def3SAnson Huang gicv3_cpuif_enable(plat_my_core_pos()); 65bd08def3SAnson Huang } 66bd08def3SAnson Huang 67bd08def3SAnson Huang void plat_gic_cpuif_disable(void) 68bd08def3SAnson Huang { 69bd08def3SAnson Huang gicv3_cpuif_disable(plat_my_core_pos()); 70bd08def3SAnson Huang } 71bd08def3SAnson Huang 72bd08def3SAnson Huang void plat_gic_pcpu_init(void) 73bd08def3SAnson Huang { 74bd08def3SAnson Huang gicv3_rdistif_init(plat_my_core_pos()); 75bd08def3SAnson Huang } 76*3a2b5199SAnson Huang 77*3a2b5199SAnson Huang void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx) 78*3a2b5199SAnson Huang { 79*3a2b5199SAnson Huang /* save the gic rdist/dist context */ 80*3a2b5199SAnson Huang for (int i = 0; i < PLATFORM_CORE_COUNT; i++) 81*3a2b5199SAnson Huang gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); 82*3a2b5199SAnson Huang gicv3_distif_save(&ctx->dist_ctx); 83*3a2b5199SAnson Huang } 84*3a2b5199SAnson Huang 85*3a2b5199SAnson Huang void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx) 86*3a2b5199SAnson Huang { 87*3a2b5199SAnson Huang /* restore the gic rdist/dist context */ 88*3a2b5199SAnson Huang gicv3_distif_init_restore(&ctx->dist_ctx); 89*3a2b5199SAnson Huang for (int i = 0; i < PLATFORM_CORE_COUNT; i++) 90*3a2b5199SAnson Huang gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); 91*3a2b5199SAnson Huang } 92