1 /* 2 * Copyright (C) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef IMX_SNVS_H 7 #define IMX_SNVS_H 8 9 #include <stdint.h> 10 11 #include <arch.h> 12 13 struct snvs { 14 uint32_t hplr; 15 uint32_t hpcomr; 16 uint32_t hpcr; 17 uint32_t hpsicr; 18 uint32_t hpsvcr; 19 uint32_t hpsr; 20 uint32_t hpsvsr; 21 uint32_t hphacivr; 22 uint32_t hphacr; 23 uint32_t hprtcmr; 24 uint32_t hprtclr; 25 uint32_t hptamr; 26 uint32_t hptalr; 27 uint32_t lplr; 28 uint32_t lpcr; 29 uint32_t lpmkcr; 30 uint32_t lpsvcr; 31 uint32_t lptgfcr; 32 uint32_t lptdcr; 33 uint32_t lpsr; 34 uint32_t lpsrtcmr; 35 uint32_t lpsrtclr; 36 uint32_t lptar; 37 uint32_t lpsmcmr; 38 uint32_t lpsmclr; 39 uint32_t lppgdr; 40 uint32_t lpgpr0_alias; 41 uint8_t lpzmkr[32]; 42 uint16_t res0; 43 uint32_t lpgpr0[4]; 44 uint32_t lptdc2r; 45 uint32_t lptdsr; 46 uint32_t lptgf1cr; 47 uint32_t lptgf2cr; 48 uint32_t res1[4]; 49 uint32_t lpat1cr; 50 uint32_t lpat2cr; 51 uint32_t lpat3cr; 52 uint32_t lpat4cr; 53 uint32_t lpat5cr; 54 uint32_t res2[3]; 55 uint32_t lpatctlr; 56 uint32_t lpatclkr; 57 uint32_t lpatrc1r; 58 uint32_t lpatrc2r; 59 uint32_t res3[706]; 60 uint32_t hpvidr1; 61 uint32_t hpvidr2; 62 } __packed; 63 64 /* Define the HPCOMR bits */ 65 #define HPCOMR_NPSWA_EN BIT(31) 66 #define HPCOMR_HAC_STOP BIT(19) 67 #define HPCOMR_HAC_CLEAR BIT(18) 68 #define HPCOMR_HAC_LOAD BIT(17) 69 #define HPCOMR_HAC_EN BIT(16) 70 #define HPCOMR_MKS_EN BIT(13) 71 #define HPCOMR_PROG_ZMK BIT(12) 72 #define HPCOMR_SW_LPSV BIT(10) 73 #define HPCOMR_SW_FSV BIT(9) 74 #define HPCOMR_SW_SV BIT(8) 75 #define HPCOMR_LP_SWR_DIS BIT(5) 76 #define HPCOMR_LP_SWR BIT(4) 77 #define HPCOMR_SSM_SFNS_DIS BIT(2) 78 #define HPCOMR_SSM_ST_DIS BIT(1) 79 #define HPCOMR_SSM_ST BIT(0) 80 81 void imx_snvs_init(void); 82 83 #endif /* IMX_SNVS_H */ 84