xref: /rk3399_ARM-atf/plat/imx/common/include/imx_sip_svc.h (revision b47dddd061e92054c3b2096fc8aa9688bfef68d6)
1 /*
2  * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __IMX_SIP_SVC_H__
8 #define __IMX_SIP_SVC_H__
9 
10 /* SMC function IDs for SiP Service queries */
11 #define IMX_SIP_GPC			0xC2000000
12 
13 #define IMX_SIP_CPUFREQ			0xC2000001
14 #define IMX_SIP_SET_CPUFREQ		0x00
15 
16 #define IMX_SIP_SRTC			0xC2000002
17 #define IMX_SIP_SRTC_SET_TIME		0x00
18 
19 #define IMX_SIP_BUILDINFO			0xC2000003
20 #define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
21 
22 #define IMX_SIP_DDR_DVFS		0xc2000004
23 
24 #define IMX_SIP_SRC			0xC2000005
25 #define IMX_SIP_SRC_SET_SECONDARY_BOOT	0x10
26 #define IMX_SIP_SRC_IS_SECONDARY_BOOT	0x11
27 
28 #define IMX_SIP_GET_SOC_INFO		0xC2000006
29 
30 #define IMX_SIP_HAB			0xC2000007
31 #define IMX_SIP_HAB_AUTH_IMG		0x00
32 #define IMX_SIP_HAB_ENTRY		0x01
33 #define IMX_SIP_HAB_EXIT		0x02
34 #define IMX_SIP_HAB_REPORT_EVENT	0x03
35 #define IMX_SIP_HAB_REPORT_STATUS	0x04
36 #define IMX_SIP_HAB_FAILSAFE		0x05
37 #define IMX_SIP_HAB_CHECK_TARGET	0x06
38 #define IMX_SIP_HAB_GET_VERSION		0x07
39 #define IMX_SIP_HAB_AUTH_IMG_NO_DCD	0x08
40 
41 #define IMX_SIP_WAKEUP_SRC		0xC2000009
42 #define IMX_SIP_WAKEUP_SRC_SCU		0x1
43 #define IMX_SIP_WAKEUP_SRC_IRQSTEER	0x2
44 
45 #define IMX_SIP_OTP_READ		0xC200000A
46 #define IMX_SIP_OTP_WRITE		0xC200000B
47 
48 #define IMX_SIP_MISC_SET_TEMP		0xC200000C
49 
50 #define IMX_SIP_AARCH32			0xC20000FD
51 
52 int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1,
53 			     u_register_t x2, u_register_t x3,
54 			     u_register_t x4);
55 
56 #define IMX_SIP_SCMI			0xC20000FE
57 
58 #define IMX_SIP_HIFI_XRDC		0xC200000E
59 
60 #if defined(PLAT_imx8mq)
61 int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
62 			 u_register_t x2, u_register_t x3);
63 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
64 		    u_register_t x2, u_register_t x3);
65 #if IMX_DRAM_RETENTION
66 int dram_dvfs_handler(uint32_t smc_fid, void *handle,
67 	u_register_t x1, u_register_t x2, u_register_t x3);
68 #else
69 static inline int dram_dvfs_handler(uint32_t smc_fid, void *handle,
70 		u_register_t x1, u_register_t x2, u_register_t x3)
71 {
72 	SMC_RET1(handle, SMC_UNK);
73 }
74 #endif
75 int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
76 	u_register_t x2, u_register_t x3, u_register_t x4);
77 #endif
78 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
79 int dram_dvfs_handler(uint32_t smc_fid, void *handle,
80 	u_register_t x1, u_register_t x2, u_register_t x3);
81 
82 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
83 		    u_register_t x2, u_register_t x3);
84 #endif
85 
86 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) || defined(PLAT_imx8mn) || \
87 	defined(PLAT_imx8mp)
88 
89 int imx_src_handler(uint32_t smc_fid, u_register_t x1,
90 		    u_register_t x2, u_register_t x3, void *handle);
91 #endif
92 
93 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
94 int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
95 		    u_register_t x2, u_register_t x3, u_register_t x4);
96 #endif
97 
98 #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
99 int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
100 			u_register_t x2, u_register_t x3);
101 int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
102 		     u_register_t x2, u_register_t x3, u_register_t x4);
103 int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1,
104 			   u_register_t x2, u_register_t x3);
105 int imx_otp_handler(uint32_t smc_fid, void *handle,
106 		    u_register_t x1, u_register_t x2);
107 int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
108 			      u_register_t x2, u_register_t x3,
109 			      u_register_t x4);
110 #endif
111 uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
112 			       u_register_t x2, u_register_t x3,
113 			       u_register_t x4);
114 int scmi_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
115 int imx_hifi_xrdc(uint32_t smc_fid);
116 
117 #if defined(PLAT_imx8ulp)
118 int dram_dvfs_handler(uint32_t smc_fid, void *handle,
119 	u_register_t x1, u_register_t x2, u_register_t x3);
120 #endif
121 
122 #endif /* __IMX_SIP_SVC_H__ */
123