1025514baSAnson Huang /* 2*fcd41e86SJacky Bai * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3025514baSAnson Huang * 4025514baSAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5025514baSAnson Huang */ 6025514baSAnson Huang 7025514baSAnson Huang #ifndef __IMX_SIP_SVC_H__ 8025514baSAnson Huang #define __IMX_SIP_SVC_H__ 9025514baSAnson Huang 10025514baSAnson Huang /* SMC function IDs for SiP Service queries */ 1144dea544SJacky Bai #define IMX_SIP_GPC 0xC2000000 1244dea544SJacky Bai 13d3996c59SAnson Huang #define IMX_SIP_CPUFREQ 0xC2000001 14d3996c59SAnson Huang #define IMX_SIP_SET_CPUFREQ 0x00 15d3996c59SAnson Huang 16025514baSAnson Huang #define IMX_SIP_SRTC 0xC2000002 17025514baSAnson Huang #define IMX_SIP_SRTC_SET_TIME 0x00 18025514baSAnson Huang 19760f7941SAnson Huang #define IMX_SIP_BUILDINFO 0xC2000003 20760f7941SAnson Huang #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 21760f7941SAnson Huang 229c336f61SJacky Bai #define IMX_SIP_DDR_DVFS 0xc2000004 239c336f61SJacky Bai 249ce232feSIgor Opaniuk #define IMX_SIP_SRC 0xC2000005 259ce232feSIgor Opaniuk #define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10 269ce232feSIgor Opaniuk #define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11 279ce232feSIgor Opaniuk 2872196cbbSLeonard Crestez #define IMX_SIP_GET_SOC_INFO 0xC2000006 2972196cbbSLeonard Crestez 30720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB 0xC2000007 31720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_AUTH_IMG 0x00 32720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_ENTRY 0x01 33720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_EXIT 0x02 34720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_REPORT_EVENT 0x03 35720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_REPORT_STATUS 0x04 36720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_FAILSAFE 0x05 37720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_CHECK_TARGET 0x06 38720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_GET_VERSION 0x07 39720e7b66SAndrey Zhizhikin #define IMX_SIP_HAB_AUTH_IMG_NO_DCD 0x08 40720e7b66SAndrey Zhizhikin 41ebdbc25bSAnson Huang #define IMX_SIP_WAKEUP_SRC 0xC2000009 42ebdbc25bSAnson Huang #define IMX_SIP_WAKEUP_SRC_SCU 0x1 43ebdbc25bSAnson Huang #define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 44ebdbc25bSAnson Huang 45dbfa45e8SAnson Huang #define IMX_SIP_OTP_READ 0xC200000A 46dbfa45e8SAnson Huang #define IMX_SIP_OTP_WRITE 0xC200000B 47dbfa45e8SAnson Huang 48869eebc3SAnson Huang #define IMX_SIP_MISC_SET_TEMP 0xC200000C 49869eebc3SAnson Huang 504a0ac3e3SPeng Fan #define IMX_SIP_AARCH32 0xC20000FD 514a0ac3e3SPeng Fan 524a0ac3e3SPeng Fan int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1, 534a0ac3e3SPeng Fan u_register_t x2, u_register_t x3, 544a0ac3e3SPeng Fan u_register_t x4); 55*fcd41e86SJacky Bai 56*fcd41e86SJacky Bai #define IMX_SIP_SCMI 0xC20000FE 57*fcd41e86SJacky Bai 5872196cbbSLeonard Crestez #if defined(PLAT_imx8mq) 5972196cbbSLeonard Crestez int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, 6072196cbbSLeonard Crestez u_register_t x2, u_register_t x3); 6188a26465SJacky Bai int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, 6288a26465SJacky Bai u_register_t x2, u_register_t x3); 638962bdd6SJacky Bai int dram_dvfs_handler(uint32_t smc_fid, void *handle, 648962bdd6SJacky Bai u_register_t x1, u_register_t x2, u_register_t x3); 6572196cbbSLeonard Crestez #endif 669c336f61SJacky Bai #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) 679c336f61SJacky Bai int dram_dvfs_handler(uint32_t smc_fid, void *handle, 689c336f61SJacky Bai u_register_t x1, u_register_t x2, u_register_t x3); 6944dea544SJacky Bai 7044dea544SJacky Bai int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, 7144dea544SJacky Bai u_register_t x2, u_register_t x3); 729c336f61SJacky Bai #endif 7372196cbbSLeonard Crestez 746d2c502aSIgor Opaniuk #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) || defined(PLAT_imx8mn) || \ 756d2c502aSIgor Opaniuk defined(PLAT_imx8mp) 766d2c502aSIgor Opaniuk 779ce232feSIgor Opaniuk int imx_src_handler(uint32_t smc_fid, u_register_t x1, 789ce232feSIgor Opaniuk u_register_t x2, u_register_t x3, void *handle); 799ce232feSIgor Opaniuk #endif 809ce232feSIgor Opaniuk 81720e7b66SAndrey Zhizhikin #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) 82720e7b66SAndrey Zhizhikin int imx_hab_handler(uint32_t smc_fid, u_register_t x1, 83720e7b66SAndrey Zhizhikin u_register_t x2, u_register_t x3, u_register_t x4); 84720e7b66SAndrey Zhizhikin #endif 85720e7b66SAndrey Zhizhikin 86f56afc1fSLeonard Crestez #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx)) 87d3996c59SAnson Huang int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1, 88d3996c59SAnson Huang u_register_t x2, u_register_t x3); 89025514baSAnson Huang int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1, 90025514baSAnson Huang u_register_t x2, u_register_t x3, u_register_t x4); 91ebdbc25bSAnson Huang int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1, 92ebdbc25bSAnson Huang u_register_t x2, u_register_t x3); 93dbfa45e8SAnson Huang int imx_otp_handler(uint32_t smc_fid, void *handle, 94dbfa45e8SAnson Huang u_register_t x1, u_register_t x2); 95869eebc3SAnson Huang int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1, 96869eebc3SAnson Huang u_register_t x2, u_register_t x3, 97869eebc3SAnson Huang u_register_t x4); 98950d05f7SLeonard Crestez #endif 99760f7941SAnson Huang uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1, 100760f7941SAnson Huang u_register_t x2, u_register_t x3, 101760f7941SAnson Huang u_register_t x4); 102*fcd41e86SJacky Bai int scmi_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); 103025514baSAnson Huang 104025514baSAnson Huang #endif /* __IMX_SIP_SVC_H__ */ 105