1025514baSAnson Huang /* 2*9c336f61SJacky Bai * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3025514baSAnson Huang * 4025514baSAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5025514baSAnson Huang */ 6025514baSAnson Huang 7025514baSAnson Huang #ifndef __IMX_SIP_SVC_H__ 8025514baSAnson Huang #define __IMX_SIP_SVC_H__ 9025514baSAnson Huang 10025514baSAnson Huang /* SMC function IDs for SiP Service queries */ 11d3996c59SAnson Huang #define IMX_SIP_CPUFREQ 0xC2000001 12d3996c59SAnson Huang #define IMX_SIP_SET_CPUFREQ 0x00 13d3996c59SAnson Huang 14025514baSAnson Huang #define IMX_SIP_SRTC 0xC2000002 15025514baSAnson Huang #define IMX_SIP_SRTC_SET_TIME 0x00 16025514baSAnson Huang 17760f7941SAnson Huang #define IMX_SIP_BUILDINFO 0xC2000003 18760f7941SAnson Huang #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 19760f7941SAnson Huang 20*9c336f61SJacky Bai #define IMX_SIP_DDR_DVFS 0xc2000004 21*9c336f61SJacky Bai 229ce232feSIgor Opaniuk #define IMX_SIP_SRC 0xC2000005 239ce232feSIgor Opaniuk #define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10 249ce232feSIgor Opaniuk #define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11 259ce232feSIgor Opaniuk 2672196cbbSLeonard Crestez #define IMX_SIP_GET_SOC_INFO 0xC2000006 2772196cbbSLeonard Crestez 28ebdbc25bSAnson Huang #define IMX_SIP_WAKEUP_SRC 0xC2000009 29ebdbc25bSAnson Huang #define IMX_SIP_WAKEUP_SRC_SCU 0x1 30ebdbc25bSAnson Huang #define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 31ebdbc25bSAnson Huang 32dbfa45e8SAnson Huang #define IMX_SIP_OTP_READ 0xC200000A 33dbfa45e8SAnson Huang #define IMX_SIP_OTP_WRITE 0xC200000B 34dbfa45e8SAnson Huang 35869eebc3SAnson Huang #define IMX_SIP_MISC_SET_TEMP 0xC200000C 36869eebc3SAnson Huang 374a0ac3e3SPeng Fan #define IMX_SIP_AARCH32 0xC20000FD 384a0ac3e3SPeng Fan 394a0ac3e3SPeng Fan int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1, 404a0ac3e3SPeng Fan u_register_t x2, u_register_t x3, 414a0ac3e3SPeng Fan u_register_t x4); 4272196cbbSLeonard Crestez #if defined(PLAT_imx8mq) 4372196cbbSLeonard Crestez int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, 4472196cbbSLeonard Crestez u_register_t x2, u_register_t x3); 4572196cbbSLeonard Crestez #endif 46*9c336f61SJacky Bai #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) 47*9c336f61SJacky Bai int dram_dvfs_handler(uint32_t smc_fid, void *handle, 48*9c336f61SJacky Bai u_register_t x1, u_register_t x2, u_register_t x3); 49*9c336f61SJacky Bai #endif 5072196cbbSLeonard Crestez 519ce232feSIgor Opaniuk #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) 529ce232feSIgor Opaniuk int imx_src_handler(uint32_t smc_fid, u_register_t x1, 539ce232feSIgor Opaniuk u_register_t x2, u_register_t x3, void *handle); 549ce232feSIgor Opaniuk #endif 559ce232feSIgor Opaniuk 56f56afc1fSLeonard Crestez #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx)) 57d3996c59SAnson Huang int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1, 58d3996c59SAnson Huang u_register_t x2, u_register_t x3); 59025514baSAnson Huang int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1, 60025514baSAnson Huang u_register_t x2, u_register_t x3, u_register_t x4); 61ebdbc25bSAnson Huang int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1, 62ebdbc25bSAnson Huang u_register_t x2, u_register_t x3); 63dbfa45e8SAnson Huang int imx_otp_handler(uint32_t smc_fid, void *handle, 64dbfa45e8SAnson Huang u_register_t x1, u_register_t x2); 65869eebc3SAnson Huang int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1, 66869eebc3SAnson Huang u_register_t x2, u_register_t x3, 67869eebc3SAnson Huang u_register_t x4); 68950d05f7SLeonard Crestez #endif 69760f7941SAnson Huang uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1, 70760f7941SAnson Huang u_register_t x2, u_register_t x3, 71760f7941SAnson Huang u_register_t x4); 72025514baSAnson Huang 73025514baSAnson Huang #endif /* __IMX_SIP_SVC_H__ */ 74