1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef IMX_CLOCK_H 7 #define IMX_CLOCK_H 8 9 #include <stdint.h> 10 #include <stdbool.h> 11 12 struct ccm_pll_ctrl { 13 uint32_t ccm_pll_ctrl; 14 uint32_t ccm_pll_ctrl_set; 15 uint32_t ccm_pll_ctrl_clr; 16 uint32_t ccm_pll_ctrl_tog; 17 }; 18 19 /* Clock gate control */ 20 struct ccm_clk_gate_ctrl { 21 uint32_t ccm_ccgr; 22 uint32_t ccm_ccgr_set; 23 uint32_t ccm_ccgr_clr; 24 uint32_t ccm_ccgr_tog; 25 }; 26 27 #define CCM_CCGR_SETTING0_DOM_CLK_NONE 0 28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0) 29 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1) 30 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0)) 31 #define CCM_CCGR_SETTING1_DOM_CLK_NONE 0 32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4) 33 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5) 34 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4)) 35 #define CCM_CCGR_SETTING2_DOM_CLK_NONE 0 36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8) 37 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9) 38 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8)) 39 #define CCM_CCGR_SETTING3_DOM_CLK_NONE 0 40 #define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12) 41 #define CCM_CCGR_SETTING3_DOM_CLK_RUN_WAIT BIT(13) 42 #define CCM_CCGR_SETTING3_DOM_CLK_ALWAYS (BIT(13) | BIT(12)) 43 44 enum { 45 CCM_CCGR_ID_ADC = 32, 46 CCM_CCGR_ID_AIPS1TZ = 10, 47 CCM_CCGR_ID_AIPS2TZ = 11, 48 CCM_CCGR_ID_AIPS3TZ = 12, 49 CCM_CCGR_ID_APBHDMA = 20, 50 CCM_CCGR_ID_CAAM = 36, 51 CCM_CCGR_ID_CM4 = 1, 52 CCM_CCGR_ID_CSI = 73, 53 CCM_CCGR_ID_CSU = 45, 54 CCM_CCGR_ID_DAP = 47, 55 CCM_CCGR_ID_DBGMON = 46, 56 CCM_CCGR_ID_DDRC = 19, 57 CCM_CCGR_ID_ECSPI1 = 120, 58 CCM_CCGR_ID_ECSPI2 = 121, 59 CCM_CCGR_ID_ECSPI3 = 122, 60 CCM_CCGR_ID_ECSPI4 = 123, 61 CCM_CCGR_ID_EIM = 22, 62 CCM_CCGR_ID_ENET1 = 112, 63 CCM_CCGR_ID_ENET2 = 113, 64 CCM_CCGR_ID_EPDC = 74, 65 CCM_CCGR_ID_FLEXCAN1 = 116, 66 CCM_CCGR_ID_FLEXCAN2 = 117, 67 CCM_CCGR_ID_FLEXTIMER1 = 128, 68 CCM_CCGR_ID_FLEXTIMER2 = 129, 69 CCM_CCGR_ID_GPIO1 = 160, 70 CCM_CCGR_ID_GPIO2 = 161, 71 CCM_CCGR_ID_GPIO3 = 162, 72 CCM_CCGR_ID_GPIO4 = 163, 73 CCM_CCGR_ID_GPIO5 = 164, 74 CCM_CCGR_ID_GPIO6 = 165, 75 CCM_CCGR_ID_GPIO7 = 166, 76 CCM_CCGR_ID_GPT1 = 124, 77 CCM_CCGR_ID_GPT2 = 125, 78 CCM_CCGR_ID_GPT3 = 126, 79 CCM_CCGR_ID_GPT4 = 127, 80 CCM_CCGR_ID_I2C1 = 136, 81 CCM_CCGR_ID_I2C2 = 137, 82 CCM_CCGR_ID_I2C3 = 138, 83 CCM_CCGR_ID_I2C4 = 139, 84 CCM_CCGR_ID_IOMUXC1 = 168, 85 CCM_CCGR_ID_IOMUXC2 = 169, 86 CCM_CCGR_ID_KPP = 120, 87 CCM_CCGR_ID_LCDIF = 75, 88 CCM_CCGR_ID_MIPI_CSI = 100, 89 CCM_CCGR_ID_MIPI_DSI = 101, 90 CCM_CCGR_ID_MIPI_PHY = 102, 91 CCM_CCGR_ID_MU = 39, 92 CCM_CCGR_ID_OCOTP = 35, 93 CCM_CCGR_ID_OCRAM = 17, 94 CCM_CCGR_ID_OCRAM_S = 18, 95 CCM_CCGR_ID_PCIE = 96, 96 CCM_CCGR_ID_PCIE_PHY = 96, 97 CCM_CCGR_ID_PERFMON1 = 68, 98 CCM_CCGR_ID_PERFMON2 = 69, 99 CCM_CCGR_ID_PWM1 = 132, 100 CCM_CCGR_ID_PWM2 = 133, 101 CCM_CCGR_ID_PWM3 = 134, 102 CCM_CCGR_ID_PMM4 = 135, 103 CCM_CCGR_ID_PXP = 76, 104 CCM_CCGR_ID_QOS1 = 42, 105 CCM_CCGR_ID_QOS2 = 43, 106 CCM_CCGR_ID_QOS3 = 44, 107 CCM_CCGR_ID_QUADSPI = 21, 108 CCM_CCGR_ID_RDC = 38, 109 CCM_CCGR_ID_ROMCP = 16, 110 CCM_CCGR_ID_SAI1 = 140, 111 CCM_CCGR_ID_SAI2 = 141, 112 CCM_CCGR_ID_SAI3 = 142, 113 CCM_CCGR_ID_SCTR = 34, 114 CCM_CCGR_ID_SDMA = 72, 115 CCM_CCGR_ID_SEC = 49, 116 CCM_CCGR_ID_SEMA42_1 = 64, 117 CCM_CCGR_ID_SEMA42_2 = 65, 118 CCM_CCGR_ID_SIM_DISPLAY = 5, 119 CCM_CCGR_ID_SIM_ENET = 6, 120 CCM_CCGR_ID_SIM_M = 7, 121 CCM_CCGR_ID_SIM_MAIN = 4, 122 CCM_CCGR_ID_SIM_S = 8, 123 CCM_CCGR_ID_SIM_WAKEUP = 9, 124 CCM_CCGR_ID_SIM1 = 144, 125 CCM_CCGR_ID_SIM2 = 145, 126 CCM_CCGR_ID_SIM_NAND = 20, 127 CCM_CCGR_ID_DISPLAY_CM4 = 1, 128 CCM_CCGR_ID_DRAM = 19, 129 CCM_CCGR_ID_SNVS = 37, 130 CCM_CCGR_ID_SPBA = 12, 131 CCM_CCGR_ID_TRACE = 48, 132 CCM_CCGR_ID_TZASC = 19, 133 CCM_CCGR_ID_UART1 = 148, 134 CCM_CCGR_ID_UART2 = 149, 135 CCM_CCGR_ID_UART3 = 150, 136 CCM_CCGR_ID_UART4 = 151, 137 CCM_CCGR_ID_UART5 = 152, 138 CCM_CCGR_ID_UART6 = 153, 139 CCM_CCGR_ID_UART7 = 154, 140 CCM_CCGR_ID_USB_HS = 40, 141 CCM_CCGR_ID_USB_IPG = 104, 142 CCM_CCGR_ID_USB_PHY_480MCLK = 105, 143 CCM_CCGR_ID_USB_OTG1_PHY = 106, 144 CCM_CCGR_ID_USB_OTG2_PHY = 107, 145 CCM_CCGR_ID_USBHDC1 = 108, 146 CCM_CCGR_ID_USBHDC2 = 109, 147 CCM_CCGR_ID_USBHDC3 = 110, 148 CCM_CCGR_ID_WDOG1 = 156, 149 CCM_CCGR_ID_WDOG2 = 157, 150 CCM_CCGR_ID_WDOG3 = 158, 151 CCM_CCGR_ID_WDOG4 = 159, 152 }; 153 154 /* Clock target block */ 155 struct ccm_target_root_ctrl { 156 uint32_t ccm_target_root; 157 uint32_t ccm_target_root_set; 158 uint32_t ccm_target_root_clr; 159 uint32_t ccm_target_root_tog; 160 uint32_t ccm_misc; 161 uint32_t ccm_misc_set; 162 uint32_t ccm_misc_clr; 163 uint32_t ccm_misc_tog; 164 uint32_t ccm_post; 165 uint32_t ccm_post_set; 166 uint32_t ccm_post_clr; 167 uint32_t ccm_post_tog; 168 uint32_t ccm_pre; 169 uint32_t ccm_pre_set; 170 uint32_t ccm_pre_clr; 171 uint32_t ccm_pre_tog; 172 uint32_t reserved[0x0c]; 173 uint32_t ccm_access_ctrl; 174 uint32_t ccm_access_ctrl_set; 175 uint32_t ccm_access_ctrl_clr; 176 uint32_t ccm_access_ctrl_tog; 177 }; 178 179 #define CCM_TARGET_ROOT_ENABLE BIT(28) 180 #define CCM_TARGET_MUX(x) (((x) - 1) << 24) 181 #define CCM_TARGET_PRE_PODF(x) (((x) - 1) << 16) 182 #define CCM_TARGET_POST_PODF(x) ((x) - 1) 183 184 /* Target root MUX values - selects the clock source for a block */ 185 /* ARM_A7_CLK_ROOT */ 186 187 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_OSC_24M 0 188 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ARM_PLL BIT(24) 189 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ENET_PLL_DIV2 BIT(25) 190 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_DDR_PLL (BIT(25) | BIT(24)) 191 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL BIT(26) 192 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL_PFD0 (BIT(26) | BIT(24)) 193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 194 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 195 196 /* ARM_M4_CLK_ROOT */ 197 198 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_OSC_24M 0 199 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 200 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_ENET_PLL_DIV4 BIT(25) 201 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_PFD2 (BIT(25) | BIT(24)) 202 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_DDR_PLL_DIV2 BIT(26) 203 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTV_IDEO_PLL (BIT(26) | BIT(25)) 205 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24)) 206 207 /* MAIN_AXI_CLK_ROOT */ 208 209 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_OSC_24M 0 210 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD1 BIT(24) 211 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 212 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24)) 213 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD5 BIT(26) 214 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 215 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 216 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 217 218 /* DISP_AXI_CLK_ROOT */ 219 220 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_OSC_24M 0 221 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD1 BIT(24) 222 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 223 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24)) 224 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD6 BIT(26) 225 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD7 (BIT(26) | BIT(24)) 226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 227 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 228 229 /* ENET_AXI_CLK_ROOT */ 230 231 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_OSC_24M 0 232 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD2 BIT(24) 233 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 234 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24)) 235 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_DIV2 BIT(26) 236 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 237 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 238 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD4 ((BIT(26) | BIT(25) | BIT(24)) 239 240 /* NAND_USDHC_BUS_CLK_ROOT */ 241 242 #define CM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_OSC_24M 0 243 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB BIT(24) 244 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 245 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_DIV2 (BIT(25) | BIT(24)) 246 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(26) 247 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(24)) 248 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25)) 249 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24)) 250 251 /* AHB_CLK_ROOT */ 252 253 #define CCM_TRGT_MUX_AHB_CLK_ROOT_OSC_24M 0 254 #define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD2 BIT(24) 255 #define CCM_TRGT_MUX_AHB_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 256 #define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD0 (BIT(25) | BIT(24)) 257 #define CCM_TRGT_MUX_AHB_CLK_ROOT_ENET_PLL_DIV8 BIT(26) 258 #define CCM_TRGT_MUX_AHB_CLK_ROOT_USB_PLL (BIT(26) | BIT(24)) 259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 260 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 261 262 /* IPG_CLK_ROOT */ 263 #define CCM_TRGT_MUX_IPG_CLK_ROOT_AHB_CLK_ROOT 0 264 265 /* DRAM_PHYM_CLK_ROOT */ 266 #define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DDR_PLL 0 267 #define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DRAM_PHYM_ALT_CLK_ROOT BIT(24) 268 269 /* DRAM_CLK_ROOT */ 270 271 #define CCM_TRGT_MUX_DRAM_CLK_ROOT_DDR_PLL 0 272 #define CCM_TRGT_MUX_DRAM_CLK_ROOT_DRAM_ALT_CLK_ROOT BIT(24) 273 274 /* DRAM_PHYM_ALT_CLK_ROOT */ 275 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_OSC_24M 0 276 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_DDR_PLL_DIV2 BIT(24) 277 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL BIT(25) 278 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24)) 279 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_USB_PLL BIT(26) 280 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL_PFD7 (BIT(26) | BIT(24)) 281 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 282 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 283 284 /* DRAM_ALT_CLK_ROOT */ 285 286 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_OSC_24M 0 287 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_DDR_PLL_DIV2 BIT(24) 288 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL BIT(25) 289 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24)) 290 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_USB_PLL BIT(26) 291 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD0 (BIT(26) | BIT(24)) 292 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 293 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD2 ((BIT(26) | BIT(25) | BIT(24)) 294 295 /* USB_HSIC_CLK_ROOT */ 296 297 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_OSC_24M 0 298 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL BIT(24) 299 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_USB_PLL BIT(25) 300 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD3 (BIT(25) | BIT(24)) 301 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD4 BIT(26) 302 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD5 (BIT(26) | BIT(24)) 303 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25)) 304 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 305 306 /* LCDIF_PIXEL_CLK_ROOT */ 307 308 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_OSC_24M 0 309 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD5 BIT(24) 310 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 311 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_EXT_CLK3 (BIT(25) | BIT(24)) 312 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD4 BIT(26) 313 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24)) 314 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 315 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 316 317 /* MIPI_DSI_CLK_ROOT */ 318 319 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_OSC_24M 0 320 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD5 BIT(24) 321 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD3 BIT(25) 322 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24)) 323 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD0_DIV2 BIT(26) 324 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_DDR_PLL_DIV2 (BIT(26) | BIT(24)) 325 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 326 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24)) 327 328 /* MIPI_CSI_CLK_ROOT */ 329 330 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_OSC_24M 0 331 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD4 BIT(24) 332 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD3 BIT(25) 333 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24)) 334 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD0_DIV2 BIT(26) 335 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_DDR_PLL_DIV2 (BIT(26) | BIT(24)) 336 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 337 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24)) 338 339 /* MIPI_DPHY_REF_CLK_ROOT */ 340 341 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_OSC_24M 0 342 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 343 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 344 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_PFD5 (BIT(25) | BIT(24)) 345 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_REF_1M BIT(26) 346 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 347 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 348 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24)) 349 350 /* SAI1_CLK_ROOT */ 351 352 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_OSC_24M 0 353 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 354 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_AUDIO_PLL BIT(25) 355 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 356 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_VIDEO_PLL BIT(26) 357 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25)) 359 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24)) 360 361 /* SAI2_CLK_ROOT */ 362 363 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_OSC_24M 0 364 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 365 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_AUDIO_PLL BIT(25) 366 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 367 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_VIDEO_PLL BIT(26) 368 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25)) 370 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24)) 371 372 /* SAI3_CLK_ROOT */ 373 374 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_OSC_24M 0 375 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 376 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_AUDIO_PLL BIT(25) 377 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 378 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_VIDEO_PLL BIT(26) 379 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25)) 381 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24)) 382 383 /* ENET1_REF_CLK_ROOT */ 384 385 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_OSC_24M 0 386 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV8 BIT(24) 387 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV20 BIT(25) 388 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV40 (BIT(25) | BIT(24)) 389 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_SYS_PLL_DIV4 BIT(26) 390 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 391 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 392 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24)) 393 394 /* ENET1_TIME_CLK_ROOT */ 395 396 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_OSC_24M 0 397 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 398 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_AUDIO_PLL BIT(25) 399 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK1 (BIT(25) | BIT(24)) 400 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK2 BIT(26) 401 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24)) 402 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25)) 403 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 404 405 /* ENET_PHY_REF_CLK_ROOT */ 406 407 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_OSC_24M 0 408 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV40 BIT(24) 409 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV20 BIT(25) 410 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV8 (BIT(25) | BIT(24)) 411 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_DDR_PLL_DIV2 BIT(26) 412 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 413 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 414 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_SYS_PLL_PFD3 ((BIT(26) | BIT(25) | BIT(24)) 415 416 /* EIM_CLK_ROOT */ 417 418 #define CCM_TRGT_MUX_EIM_CLK_ROOT_OSC_24M 0 419 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 420 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 421 #define CCM_TRGT_MUX_EIM_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 422 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2 BIT(26) 423 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD3 (BIT(26) | BIT(24)) 424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25)) 425 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 426 427 /* NAND_CLK_ROOT */ 428 429 #define CCM_TRGT_MUX_NAND_CLK_ROOT_OSC_24M 0 430 #define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL BIT(24) 431 #define CCM_TRGT_MUX_NAND_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 432 #define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD0 (BIT(25) | BIT(24)) 433 #define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD3 BIT(26) 434 #define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV2 (BIT(26) | BIT(24)) 435 #define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25)) 436 #define CCM_TRGT_MUX_NAND_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 437 438 /* QSPI_CLK_ROOT */ 439 440 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_OSC_24M 0 441 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD4 BIT(24) 442 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 443 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24)) 444 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD3 BIT(26) 445 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24)) 446 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25)) 447 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 448 449 /* USDHC1_CLK_ROOT */ 450 451 #define CM_TRGT_MUX_USDHC1_CLK_ROOT_OSC_24M 0 452 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD0 BIT(24) 453 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 454 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24)) 455 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD4 BIT(26) 456 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24)) 457 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25)) 458 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 459 460 /* USDHC2_CLK_ROOT */ 461 462 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_OSC_24M 0 463 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD0 BIT(24) 464 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 465 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24)) 466 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD4 BIT(26) 467 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24)) 468 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25)) 469 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 470 471 /* USDHC3_CLK_ROOT */ 472 473 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_OSC_24M 0 474 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD0 BIT(24) 475 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 476 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24)) 477 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD4 BIT(26) 478 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24)) 479 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25)) 480 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 481 482 /* CAN1_CLK_ROOT */ 483 484 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_OSC_24M 0 485 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 486 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 487 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24)) 488 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_ENET_PLL_DIV25 BIT(26) 489 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_USB_PLL (BIT(26) | BIT(24)) 490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(25)) 491 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24)) 492 493 /* CAN2_CLK_ROOT */ 494 495 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_OSC_24M 0 496 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 497 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_DDR_PLL_DIV2 BIT(25) 498 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24)) 499 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_ENET_PLL_DIV25 BIT(26) 500 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_USB_PLL (BIT(26) | BIT(24)) 501 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(25)) 502 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24)) 503 504 /* I2C1_CLK_ROOT */ 505 506 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_OSC_24M 0 507 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 508 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_ENET_PLL_DIV20 BIT(25) 509 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 510 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_AUDIO_PLL BIT(26) 511 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24)) 512 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_USB_PLL (BIT(26) | BIT(25)) 513 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24)) 514 515 /* I2C2_CLK_ROOT */ 516 517 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_OSC_24M 0 518 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 519 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_ENET_PLL_DIV20 BIT(25) 520 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 521 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_AUDIO_PLL BIT(26) 522 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24)) 523 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_USB_PLL (BIT(26) | BIT(25)) 524 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24)) 525 526 /* I2C3_CLK_ROOT */ 527 528 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_OSC_24M 0 529 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 530 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_ENET_PLL_DIV20 BIT(25) 531 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 532 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_AUDIO_PLL BIT(26) 533 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24)) 534 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_USB_PLL (BIT(26) | BIT(25)) 535 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24)) 536 537 /* I2C4_CLK_ROOT */ 538 539 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_OSC_24M 0 540 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_DIV4 BIT(24) 541 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_ENET_PLL_DIV20 BIT(25) 542 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 543 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_AUDIO_PLL BIT(26) 544 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24)) 545 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_USB_PLL (BIT(26) | BIT(25)) 546 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24)) 547 548 /* UART1_CLK_ROOT */ 549 550 #define CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M 0 551 #define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 552 #define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 553 #define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 554 #define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL BIT(26) 555 #define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 556 #define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25)) 557 #define CCM_TRGT_MUX_UART1_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 558 559 /* UART2_CLK_ROOT */ 560 561 #define CCM_TRGT_MUX_UART2_CLK_ROOT_OSC_24M 0 562 #define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 563 #define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 564 #define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 565 #define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL BIT(26) 566 #define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 567 #define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25)) 568 #define CCM_TRGT_MUX_UART2_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 569 570 /* UART3_CLK_ROOT */ 571 572 #define CCM_TRGT_MUX_UART3_CLK_ROOT_OSC_24M 0 573 #define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 574 #define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 575 #define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 576 #define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL BIT(26) 577 #define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 578 #define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25)) 579 #define CCM_TRGT_MUX_UART3_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 580 581 /* UART4_CLK_ROOT */ 582 583 #define CCM_TRGT_MUX_UART4_CLK_ROOT_OSC_24M 0 584 #define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 585 #define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 586 #define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 587 #define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL BIT(26) 588 #define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 589 #define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25)) 590 #define CCM_TRGT_MUX_UART4_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 591 592 /* UART5_CLK_ROOT */ 593 594 #define CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M 0 595 #define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 596 #define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 597 #define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 598 #define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL BIT(26) 599 #define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 600 #define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25)) 601 #define CCM_TRGT_MUX_UART5_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 602 603 /* UART6_CLK_ROOT */ 604 605 #define CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M 0 606 #define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 607 #define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 608 #define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 609 #define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL BIT(26) 610 #define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 611 #define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25)) 612 #define CCM_TRGT_MUX_UART6_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 613 614 /* UART7_CLK_ROOT */ 615 616 #define CCM_TRGT_MUX_UART7_CLK_ROOT_OSC_24M 0 617 #define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 618 #define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 619 #define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24)) 620 #define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL BIT(26) 621 #define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 622 #define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25)) 623 #define CCM_TRGT_MUX_UART7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 624 625 /* ECSPI1_CLK_ROOT */ 626 627 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_OSC_24M 0 628 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 629 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 630 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24)) 631 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL BIT(26) 632 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 633 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25)) 634 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 635 636 /* ECSPI2_CLK_ROOT */ 637 638 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_OSC_24M 0 639 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 640 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 641 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24)) 642 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL BIT(26) 643 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 644 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25)) 645 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 646 647 /* ECSPI3_CLK_ROOT */ 648 649 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_OSC_24M 0 650 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 651 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 652 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24)) 653 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL BIT(26) 654 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 655 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25)) 656 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 657 658 /* ECSPI4_CLK_ROOT */ 659 660 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_OSC_24M 0 661 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV2 BIT(24) 662 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV25 BIT(25) 663 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24)) 664 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL BIT(26) 665 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24)) 666 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25)) 667 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 668 669 /* PWM1_CLK_ROOT */ 670 671 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_OSC_24M 0 672 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 673 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 674 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 675 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_AUDIO_PLL BIT(26) 676 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(24)) 677 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 678 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 679 680 /* PWM2_CLK_ROOT */ 681 682 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_OSC_24M 0 683 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 684 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 685 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 686 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_AUDIO_PLL BIT(26) 687 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(24)) 688 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 689 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 690 691 /* PWM3_CLK_ROOT */ 692 693 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_OSC_24M 0 694 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 695 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 696 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 697 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_AUDIO_PLL BIT(26) 698 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 699 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 700 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 701 702 /* PWM4_CLK_ROOT */ 703 704 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_OSC_24M 0 705 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 706 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 707 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 708 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_AUDIO_PLL BIT(26) 709 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24)) 710 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 711 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 712 713 /* FLEXTIMER1_CLK_ROOT */ 714 715 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_OSC_24M 0 716 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 717 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 718 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 719 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_AUDIO_PLL BIT(26) 720 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24)) 721 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 722 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 723 724 /* FLEXTIMER2_CLK_ROOT */ 725 726 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_OSC_24M 0 727 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 728 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 729 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 730 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_AUDIO_PLL BIT(26) 731 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24)) 732 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 733 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24)) 734 735 /* Target SIM1_CLK_ROOT */ 736 737 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_OSC_24M 0 738 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 739 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 740 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 741 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_USB_PLL BIT(26) 742 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 743 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25)) 744 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 745 746 /* Target SIM2_CLK_ROOT */ 747 748 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_OSC_24M 0 749 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 750 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 751 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 752 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_USB_PLL BIT(26) 753 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24)) 754 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25)) 755 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24)) 756 757 /* Target GPT1_CLK_ROOT */ 758 759 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_OSC_24M 0 760 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 761 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_SYS_PLL_PFD0 BIT(25) 762 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 763 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_VIDEO_PLL BIT(26) 764 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_REF_1M (BIT(26) | BIT(24)) 765 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 766 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_EXT_CLK1 ((BIT(26) | BIT(25) | BIT(24)) 767 768 /* Target GPT2_CLK_ROOT */ 769 770 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_OSC_24M 0 771 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 772 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_SYS_PLL_PFD0 BIT(25) 773 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 774 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_VIDEO_PLL BIT(26) 775 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_REF_1M (BIT(26) | BIT(24)) 776 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 777 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24)) 778 779 /* Target GPT3_CLK_ROOT */ 780 781 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_OSC_24M 0 782 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 783 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_SYS_PLL_PFD0 BIT(25) 784 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 785 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_VIDEO_PLL BIT(26) 786 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_REF_1M (BIT(26) | BIT(24)) 787 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 788 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24)) 789 790 /*Target GPT4_CLK_ROOT */ 791 792 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_OSC_24M 0 793 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV10 BIT(24) 794 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_SYS_PLL_PFD0 BIT(25) 795 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24)) 796 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_VIDEO_PLL BIT(26) 797 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_REF_1M (BIT(26) | BIT(24)) 798 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25)) 799 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24)) 800 801 /* Target TRACE_CLK_ROOT */ 802 803 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_OSC_24M 0 804 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 805 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 806 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 807 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_ENET_PLL_DIV8 BIT(26) 808 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_USB_PLL (BIT(26) | BIT(24)) 809 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(25)) 810 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24)) 811 812 /* Target WDOG_CLK_ROOT */ 813 814 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M 0 815 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 816 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 817 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 818 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_ENET_PLL_DIV8 BIT(26) 819 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL (BIT(26) | BIT(24)) 820 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M (BIT(26) | BIT(25)) 821 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2 ((BIT(26) | BIT(25) | BIT(24)) 822 823 /* Target CSI_MCLK_CLK_ROOT */ 824 825 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_OSC_24M 0 826 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 827 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 828 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 829 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_ENET_PLL_DIV8 BIT(26) 830 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 831 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 832 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 833 834 /* Target AUDIO_MCLK_CLK_ROOT */ 835 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_OSC_24M 0 836 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24) 837 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_DIV4 BIT(25) 838 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24)) 839 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_ENET_PLL_DIV8 BIT(26) 840 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24)) 841 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25)) 842 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24)) 843 844 /* Target CCM_CLKO1 */ 845 #define CCM_TRGT_MUX_CCM_CLKO1_OSC_24M 0 846 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL BIT(24) 847 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_DIV2 BIT(25) 848 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD0_DIV2 (BIT(25) | BIT(24)) 849 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD3 BIT(26) 850 #define CCM_TRGT_MUX_CCM_CLKO1_ENET_PLL_DIV2 (BIT(26) | BIT(24)) 851 #define CCM_TRGT_MUX_CCM_CLKO1_DDR_PLL_DIV2 (BIT(26) | BIT(25)) 852 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24)) 853 854 /* Target CCM_CLKO2 */ 855 #define CCM_TRGT_MUX_CCM_CLKO2_OSC_24M 0 856 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_DIV2 BIT(24) 857 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD0 BIT(25) 858 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD1_DIV2 (BIT(25) | BIT(24)) 859 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD4 BIT(26) 860 #define CCM_TRGT_MUX_CCM_CLKO2_AUDIO_PLL (BIT(26) | BIT(24)) 861 #define CCM_TRGT_MUX_CCM_CLKO2_VIDEO_PLL (BIT(26) | BIT(25)) 862 #define CCM_TRGT_MUX_CCM_CLKO2_OSC_32K ((BIT(26) | BIT(25) | BIT(24)) 863 864 /* 865 * See Table 5-11 in i.MX7 Solo Reference manual rev 0.1 866 * The indices must be calculated by dividing the offset by 867 * sizeof (struct ccm_target_root_ctrl) => 0x80 bytes for each index 868 */ 869 enum { 870 CCM_TRT_ID_ARM_A7_CLK_ROOT = 0, 871 CCM_TRT_ID_ARM_M4_CLK_ROOT = 1, 872 CCM_TRT_ID_MAIN_AXI_CLK_ROOT = 16, 873 CCM_TRT_ID_DISP_AXI_CLK_ROOT = 17, 874 CCM_TRT_ID_ENET_AXI_CLK_ROOT = 18, 875 CCM_TRT_ID_NAND_USDHC_BUS_CLK_ROOT = 19, 876 CCM_TRT_ID_AHB_CLK_ROOT = 32, 877 CCM_TRT_ID_IPG_CLK_ROOT = 33, 878 CCM_TRT_ID_DRAM_PHYM_CLK_ROOT = 48, 879 CCM_TRT_ID_DRAM_CLK_ROOT = 49, 880 CCM_TRT_ID_DRAM_PHYM_ALT_CLK_ROOT = 64, 881 CCM_TRT_ID_DRAM_ALT_CLK_ROOT = 65, 882 CCM_TRT_ID_USB_HSIC_CLK_ROOT = 66, 883 CCM_TRT_ID_LCDIF_PIXEL_CLK_ROOT = 70, 884 CCM_TRT_ID_MIPI_DSI_CLK_ROOT = 71, 885 CCM_TRT_ID_MIPI_CSI_CLK_ROOT = 72, 886 CCM_TRT_ID_MIPI_DPHY_REF_CLK_ROOT = 73, 887 CCM_TRT_ID_SAI1_CLK_ROOT = 74, 888 CCM_TRT_ID_SAI2_CLK_ROOT = 75, 889 CCM_TRT_ID_SAI3_CLK_ROOT = 76, 890 CCM_TRT_ID_ENET1_REF_CLK_ROOT = 78, 891 CCM_TRT_ID_ENET1_TIME_CLK_ROOT = 79, 892 CCM_TRT_ID_ENET_PHY_REF_CLK_ROOT = 82, 893 CCM_TRT_ID_EIM_CLK_ROOT = 83, 894 CCM_TRT_ID_NAND_CLK_ROOT = 84, 895 CCM_TRT_ID_QSPI_CLK_ROOT = 85, 896 CCM_TRT_ID_USDHC1_CLK_ROOT = 86, 897 CCM_TRT_ID_USDHC2_CLK_ROOT = 87, 898 CCM_TRT_ID_USDHC3_CLK_ROOT = 88, 899 CCM_TRT_ID_CAN1_CLK_ROOT = 89, 900 CCM_TRT_ID_CAN2_CLK_ROOT = 90, 901 CCM_TRT_ID_I2C1_CLK_ROOT = 91, 902 CCM_TRT_ID_I2C2_CLK_ROOT = 92, 903 CCM_TRT_ID_I2C3_CLK_ROOT = 93, 904 CCM_TRT_ID_I2C4_CLK_ROOT = 94, 905 CCM_TRT_ID_UART1_CLK_ROOT = 95, 906 CCM_TRT_ID_UART2_CLK_ROOT = 96, 907 CCM_TRT_ID_UART3_CLK_ROOT = 97, 908 CCM_TRT_ID_UART4_CLK_ROOT = 98, 909 CCM_TRT_ID_UART5_CLK_ROOT = 99, 910 CCM_TRT_ID_UART6_CLK_ROOT = 100, 911 CCM_TRT_ID_UART7_CLK_ROOT = 101, 912 CCM_TRT_ID_ECSPI1_CLK_ROOT = 102, 913 CCM_TRT_ID_ECSPI2_CLK_ROOT = 103, 914 CCM_TRT_ID_ECSPI3_CLK_ROOT = 104, 915 CCM_TRT_ID_ECSPI4_CLK_ROOT = 105, 916 CCM_TRT_ID_PWM1_CLK_ROOT = 106, 917 CCM_TRT_ID_PWM2_CLK_ROOT = 107, 918 CCM_TRT_ID_PWM3_CLK_ROOT = 108, 919 CCM_TRT_ID_PWM4_CLK_ROOT = 109, 920 CCM_TRT_ID_FLEXTIMER1_CLK_ROOT = 110, 921 CCM_TRT_ID_FLEXTIMER2_CLK_ROOT = 111, 922 CCM_TRT_ID_SIM1_CLK_ROOT = 112, 923 CCM_TRT_ID_SIM2_CLK_ROOT = 113, 924 CCM_TRT_ID_GPT1_CLK_ROOT = 114, 925 CCM_TRT_ID_GPT2_CLK_ROOT = 115, 926 CCM_TRT_ID_GPT3_CLK_ROOT = 116, 927 CCM_TRT_ID_GPT4_CLK_ROOT = 117, 928 CCM_TRT_ID_TRACE_CLK_ROOT = 118, 929 CCM_TRT_ID_WDOG_CLK_ROOT = 119, 930 CCM_TRT_ID_CSI_MCLK_CLK_ROOT = 120, 931 CCM_TRT_ID_AUDIO_MCLK_CLK_ROOT = 121, 932 CCM_TRT_ID_CCM_CLKO1 = 123, 933 CCM_TRT_ID_CCM_CLKO2 = 124, 934 }; 935 936 #define CCM_MISC_VIOLATE BIT(8) 937 #define CCM_MISC_TIMEOUT BIT(4) 938 #define CCM_MISC_AUTHEN_FAIL BIT(0) 939 940 #define CCM_POST_BUSY2 BIT(31) 941 #define CCM_POST_SELECT_BRANCH_A BIT(28) 942 #define CCM_POST_BUSY1 BIT(7) 943 #define CCM_POST_POST_PODF(x) ((x) - 1) 944 945 #define CCM_PRE_BUSY4 BIT(31) 946 #define CCM_PRE_ENABLE_A BIT(28) 947 #define CCM_PRE_MUX_A(x) (((x) - 1) << 24) 948 #define CCM_PRE_BUSY3 BIT(19) 949 #define CCM_PRE_PODF_A(x) (((x) - 1) << 16) 950 #define CCM_PRE_BUSY1 BIT(15) 951 #define CCM_PRE_ENABLE_B BIT(12) 952 #define CCM_PRE_MUX_B(x) (((x) - 1) << 8) 953 #define CCM_PRE_BUSY0 BIT(3) 954 #define CCM_PRE_POST_PODF(x) ((x) - 1) 955 956 #define CCM_ACCESS_CTRL_LOCK BIT(31) 957 #define CCM_ACCESS_SEMA_ENABLE BIT(28) 958 #define CCM_ACCESS_DOM3_WHITELIST BIT(27) 959 #define CCM_ACCESS_DOM2_WHITELIST BIT(26) 960 #define CCM_ACCESS_DOM1_WHITELIST BIT(25) 961 #define CCM_ACCESS_DOM0_WHITELIST BIT(24) 962 #define CCM_ACCESS_MUTEX BIT(20) 963 #define CCM_ACCESS_OWNER_ID(x) ((x) << 16) 964 #define CCM_ACCESS_DOM3_INFO(x) ((x) << 12) 965 #define CCM_ACCESS_DOM2_INFO(x) ((x) << 8) 966 #define CCM_ACCESS_DOM1_INFO(x) ((x) << 4) 967 #define CCM_ACCESS_DOM0_INFO(x) (x) 968 969 #define CCM_PLL_CTRL_NUM 0x21 970 #define CCM_CLK_GATE_CTRL_NUM 0xbf 971 #define CCM_ROOT_CTRL_NUM 0x79 972 973 struct ccm { 974 uint32_t ccm_gpr0; 975 uint32_t ccm_gpr0_set; 976 uint32_t ccm_gpr0_clr; 977 uint32_t ccm_grp0_tog; 978 uint32_t reserved[0x1fc]; 979 struct ccm_pll_ctrl ccm_pll_ctrl[CCM_PLL_CTRL_NUM]; 980 uint32_t reserved1[0xd7c]; 981 struct ccm_clk_gate_ctrl ccm_clk_gate_ctrl[CCM_CLK_GATE_CTRL_NUM]; 982 uint32_t reserved2[0xd04]; 983 struct ccm_target_root_ctrl ccm_root_ctrl[CCM_ROOT_CTRL_NUM]; 984 }; 985 986 void imx_clock_target_set(unsigned int id, uint32_t val); 987 void imx_clock_target_clr(unsigned int id, uint32_t val); 988 void imx_clock_gate_enable(unsigned int id, bool enable); 989 990 void imx_clock_init(void); 991 992 void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits); 993 void imx_clock_disable_uart(unsigned int uart_id); 994 void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits); 995 void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits); 996 void imx_clock_enable_wdog(unsigned int wdog_id); 997 void imx_clock_disable_wdog(unsigned int wdog_id); 998 void imx_clock_enable_usb(unsigned int usb_id); 999 void imx_clock_disable_usb(unsigned int usb_id); 1000 void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits); 1001 1002 #endif /* IMX_CLOCK_H */ 1003