1*bd08def3SAnson Huang /* 2*bd08def3SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*bd08def3SAnson Huang * 4*bd08def3SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5*bd08def3SAnson Huang */ 6*bd08def3SAnson Huang 7*bd08def3SAnson Huang #include <arch.h> 8*bd08def3SAnson Huang #include <arch_helpers.h> 9*bd08def3SAnson Huang #include <platform.h> 10*bd08def3SAnson Huang 11*bd08def3SAnson Huang const unsigned char imx_power_domain_tree_desc[] = { 12*bd08def3SAnson Huang PWR_DOMAIN_AT_MAX_LVL, 13*bd08def3SAnson Huang PLATFORM_CLUSTER_COUNT, 14*bd08def3SAnson Huang PLATFORM_CORE_COUNT, 15*bd08def3SAnson Huang }; 16*bd08def3SAnson Huang 17*bd08def3SAnson Huang const unsigned char *plat_get_power_domain_tree_desc(void) 18*bd08def3SAnson Huang { 19*bd08def3SAnson Huang return imx_power_domain_tree_desc; 20*bd08def3SAnson Huang } 21*bd08def3SAnson Huang 22*bd08def3SAnson Huang int plat_core_pos_by_mpidr(u_register_t mpidr) 23*bd08def3SAnson Huang { 24*bd08def3SAnson Huang unsigned int cluster_id, cpu_id; 25*bd08def3SAnson Huang 26*bd08def3SAnson Huang mpidr &= MPIDR_AFFINITY_MASK; 27*bd08def3SAnson Huang 28*bd08def3SAnson Huang if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) 29*bd08def3SAnson Huang return -1; 30*bd08def3SAnson Huang 31*bd08def3SAnson Huang cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 32*bd08def3SAnson Huang cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 33*bd08def3SAnson Huang 34*bd08def3SAnson Huang if (cluster_id > PLATFORM_CLUSTER_COUNT || 35*bd08def3SAnson Huang cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) 36*bd08def3SAnson Huang return -1; 37*bd08def3SAnson Huang 38*bd08def3SAnson Huang return (cpu_id + (cluster_id * 4)); 39*bd08def3SAnson Huang } 40