1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <context.h> 15 #include <lib/el3_runtime/context_mgmt.h> 16 #include <lib/mmio.h> 17 #include <lib/psci/psci.h> 18 #include <plat/common/platform.h> 19 20 #include "hi3798cv200.h" 21 #include "plat_private.h" 22 23 #define REG_PERI_CPU_RVBARADDR 0xF8A80034 24 #define REG_PERI_CPU_AARCH_MODE 0xF8A80030 25 26 #define REG_CPU_LP_CPU_SW_BEGIN 10 27 #define CPU_REG_COREPO_SRST 12 28 #define CPU_REG_CORE_SRST 8 29 30 static void poplar_cpu_standby(plat_local_state_t cpu_state) 31 { 32 dsb(); 33 wfi(); 34 } 35 36 static int poplar_pwr_domain_on(u_register_t mpidr) 37 { 38 unsigned int cpu = plat_core_pos_by_mpidr(mpidr); 39 unsigned int regval, regval_bak; 40 41 /* Select 400MHz before start slave cores */ 42 regval_bak = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP)); 43 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x206); 44 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x606); 45 46 /* Clear the slave cpu arm_por_srst_req reset */ 47 regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST)); 48 regval &= ~(1 << (cpu + CPU_REG_COREPO_SRST)); 49 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); 50 51 /* Clear the slave cpu reset */ 52 regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST)); 53 regval &= ~(1 << (cpu + CPU_REG_CORE_SRST)); 54 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); 55 56 /* Restore cpu frequency */ 57 regval = regval_bak & (~(1 << REG_CPU_LP_CPU_SW_BEGIN)); 58 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval); 59 mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval_bak); 60 61 return PSCI_E_SUCCESS; 62 } 63 64 static void poplar_pwr_domain_off(const psci_power_state_t *target_state) 65 { 66 assert(0); 67 } 68 69 static void poplar_pwr_domain_suspend(const psci_power_state_t *target_state) 70 { 71 assert(0); 72 } 73 74 static void poplar_pwr_domain_on_finish(const psci_power_state_t *target_state) 75 { 76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 77 PLAT_MAX_OFF_STATE); 78 79 /* Enable the gic cpu interface */ 80 poplar_gic_pcpu_init(); 81 82 /* Program the gic per-cpu distributor or re-distributor interface */ 83 poplar_gic_cpuif_enable(); 84 } 85 86 static void poplar_pwr_domain_suspend_finish( 87 const psci_power_state_t *target_state) 88 { 89 assert(0); 90 } 91 92 static void __dead2 poplar_system_off(void) 93 { 94 ERROR("Poplar System Off: operation not handled.\n"); 95 /* Turn off watchdog0 before panic() */ 96 mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0xc00), 0x1ACCE551); 97 mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x8), 0x00000000); 98 panic(); 99 } 100 101 static void __dead2 poplar_system_reset(void) 102 { 103 /* Unlock Sysctrl critical registers */ 104 mmio_write_32((uintptr_t)(REG_BASE_SCTL + REG_SC_LOCKEN), SC_UNLOCK_MAGIC); 105 /* Assert system reset */ 106 mmio_write_32((uintptr_t)(REG_BASE_SCTL + REG_SC_SYSRES), 0xfee1dead); 107 108 wfi(); 109 ERROR("Poplar System Reset: operation not handled.\n"); 110 panic(); 111 } 112 113 static int32_t poplar_validate_power_state(unsigned int power_state, 114 psci_power_state_t *req_state) 115 { 116 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 117 118 int pstate = psci_get_pstate_type(power_state); 119 120 assert(req_state); 121 122 /* Sanity check the requested state */ 123 if (pstate == PSTATE_TYPE_STANDBY) 124 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 125 else 126 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 127 128 /* We expect the 'state id' to be zero */ 129 if (psci_get_pstate_id(power_state)) 130 return PSCI_E_INVALID_PARAMS; 131 132 return PSCI_E_SUCCESS; 133 } 134 135 static int poplar_validate_ns_entrypoint(uintptr_t entrypoint) 136 { 137 /* 138 * Check if the non secure entrypoint lies within the non 139 * secure DRAM. 140 */ 141 if ((entrypoint >= DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE))) 142 return PSCI_E_SUCCESS; 143 144 return PSCI_E_INVALID_ADDRESS; 145 } 146 147 static void poplar_get_sys_suspend_power_state(psci_power_state_t *req_state) 148 { 149 int i; 150 151 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 152 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 153 } 154 155 static const plat_psci_ops_t poplar_plat_psci_ops = { 156 .cpu_standby = poplar_cpu_standby, 157 .pwr_domain_on = poplar_pwr_domain_on, 158 .pwr_domain_off = poplar_pwr_domain_off, 159 .pwr_domain_suspend = poplar_pwr_domain_suspend, 160 .pwr_domain_on_finish = poplar_pwr_domain_on_finish, 161 .pwr_domain_suspend_finish = poplar_pwr_domain_suspend_finish, 162 .system_off = poplar_system_off, 163 .system_reset = poplar_system_reset, 164 .validate_power_state = poplar_validate_power_state, 165 .validate_ns_entrypoint = poplar_validate_ns_entrypoint, 166 .get_sys_suspend_power_state = poplar_get_sys_suspend_power_state, 167 }; 168 169 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 170 const plat_psci_ops_t **psci_ops) 171 { 172 *psci_ops = &poplar_plat_psci_ops; 173 174 mmio_write_32((uintptr_t)REG_PERI_CPU_AARCH_MODE, 0xF); 175 mmio_write_32((uintptr_t)REG_PERI_CPU_RVBARADDR, sec_entrypoint); 176 return 0; 177 } 178