1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <tbbr/tbbr_img_def.h> 13 #include "hi3798cv200.h" 14 #include "poplar_layout.h" /* BL memory region sizes, etc */ 15 16 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 17 #define PLATFORM_LINKER_ARCH aarch64 18 19 #define PLAT_ARM_CRASH_UART_BASE PL011_UART0_BASE 20 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ 21 #define ARM_CONSOLE_BAUDRATE PL011_BAUDRATE 22 23 /* Generic platform constants */ 24 #define PLATFORM_STACK_SIZE (0x800) 25 26 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 27 #define BOOT_EMMC_NAME "l-loader.bin" 28 29 #define PLATFORM_CACHE_LINE_SIZE (64) 30 #define PLATFORM_CLUSTER_COUNT (1) 31 #define PLATFORM_CORE_COUNT (4) 32 #define PLATFORM_MAX_CPUS_PER_CLUSTER (4) 33 34 /* IO framework user */ 35 #define MAX_IO_DEVICES (4) 36 #define MAX_IO_HANDLES (4) 37 #define MAX_IO_BLOCK_DEVICES (2) 38 39 /* Memory map related constants */ 40 #define DDR_BASE (0x00000000) 41 #define DDR_SIZE (0x40000000) 42 43 #define DEVICE_BASE (0xF0000000) 44 #define DEVICE_SIZE (0x0F000000) 45 46 #define TEE_SEC_MEM_BASE (0x70000000) 47 #define TEE_SEC_MEM_SIZE (0x10000000) 48 49 #define BL_MEM_BASE (BL1_RO_BASE) 50 #define BL_MEM_LIMIT (BL31_LIMIT) 51 #define BL_MEM_SIZE (BL_MEM_LIMIT - BL_MEM_BASE) 52 53 #define PLAT_ARM_NS_IMAGE_OFFSET 0x37000000 54 55 /* Page table and MMU setup constants */ 56 #define ADDR_SPACE_SIZE (1ull << 32) 57 #define MAX_XLAT_TABLES (4) 58 #define MAX_MMAP_REGIONS (16) 59 60 #define CACHE_WRITEBACK_SHIFT (6) 61 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 62 63 /* Power states */ 64 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1) 65 #define PLAT_MAX_OFF_STATE 2 66 #define PLAT_MAX_RET_STATE 1 67 68 /* Interrupt controller */ 69 #define PLAT_ARM_GICD_BASE GICD_BASE 70 #define PLAT_ARM_GICC_BASE GICC_BASE 71 72 #define PLAT_ARM_G1S_IRQS HISI_IRQ_SEC_SGI_0, \ 73 HISI_IRQ_SEC_SGI_1, \ 74 HISI_IRQ_SEC_SGI_2, \ 75 HISI_IRQ_SEC_SGI_3, \ 76 HISI_IRQ_SEC_SGI_4, \ 77 HISI_IRQ_SEC_SGI_5, \ 78 HISI_IRQ_SEC_SGI_6, \ 79 HISI_IRQ_SEC_SGI_7, \ 80 HISI_IRQ_SEC_TIMER0, \ 81 HISI_IRQ_SEC_TIMER1, \ 82 HISI_IRQ_SEC_TIMER2, \ 83 HISI_IRQ_SEC_TIMER3, \ 84 HISI_IRQ_SEC_AXI 85 86 #define PLAT_ARM_G0_IRQS 87 88 #endif /* __PLATFORM_DEF_H__ */ 89