1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <gic_common.h> 13 #include <interrupt_props.h> 14 #include <tbbr/tbbr_img_def.h> 15 #include <utils_def.h> 16 #include "hi3798cv200.h" 17 #include "poplar_layout.h" /* BL memory region sizes, etc */ 18 19 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 20 #define PLATFORM_LINKER_ARCH aarch64 21 22 #define PLAT_ARM_CRASH_UART_BASE PL011_UART0_BASE 23 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ 24 #define ARM_CONSOLE_BAUDRATE PL011_BAUDRATE 25 26 /* Generic platform constants */ 27 #define PLATFORM_STACK_SIZE (0x800) 28 29 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 30 #define BOOT_EMMC_NAME "l-loader.bin" 31 32 #define PLATFORM_CACHE_LINE_SIZE (64) 33 #define PLATFORM_CLUSTER_COUNT (1) 34 #define PLATFORM_CORE_COUNT (4) 35 #define PLATFORM_MAX_CPUS_PER_CLUSTER (4) 36 37 /* IO framework user */ 38 #define MAX_IO_DEVICES (4) 39 #define MAX_IO_HANDLES (4) 40 #define MAX_IO_BLOCK_DEVICES (2) 41 42 /* Memory map related constants */ 43 #define DDR_BASE (0x00000000) 44 #define DDR_SIZE (0x40000000) 45 46 #define DEVICE_BASE (0xF0000000) 47 #define DEVICE_SIZE (0x0F000000) 48 49 #define TEE_SEC_MEM_BASE (0x70000000) 50 #define TEE_SEC_MEM_SIZE (0x10000000) 51 52 /* Memory location options for TSP */ 53 #define POPLAR_SRAM_ID 0 54 #define POPLAR_DRAM_ID 1 55 56 /* 57 * DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several 58 * regions: 59 * - Secure DDR (default is the top 16MB) used by OP-TEE 60 * - Non-secure DDR (4MB) reserved for OP-TEE's future use 61 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 62 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 63 */ 64 #define DDR_SEC_SIZE 0x01000000 65 #define DDR_SEC_BASE 0x03000000 66 67 #define BL_MEM_BASE (BL1_RO_BASE) 68 #define BL_MEM_LIMIT (BL31_LIMIT) 69 #define BL_MEM_SIZE (BL_MEM_LIMIT - BL_MEM_BASE) 70 71 /* 72 * BL3-2 specific defines. 73 */ 74 75 /* 76 * The TSP currently executes from TZC secured area of DRAM. 77 */ 78 #define BL32_DRAM_BASE 0x03000000 79 #define BL32_DRAM_LIMIT 0x04000000 80 81 #if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID) 82 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 83 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 84 #define BL32_BASE BL32_DRAM_BASE 85 #define BL32_LIMIT BL32_DRAM_LIMIT 86 #elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID) 87 #error "SRAM storage of TSP payload is currently unsupported" 88 #else 89 #error "Currently unsupported POPLAR_TSP_LOCATION_ID value" 90 #endif 91 92 /* BL32 is mandatory in AArch32 */ 93 #ifndef AARCH32 94 #ifdef SPD_none 95 #undef BL32_BASE 96 #endif /* SPD_none */ 97 #endif 98 99 #define POPLAR_EMMC_DATA_BASE U(0x02200000) 100 #define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE 101 #define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE) 102 #define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE 103 104 #define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000 105 106 /* Page table and MMU setup constants */ 107 #define ADDR_SPACE_SIZE (1ull << 32) 108 #define MAX_XLAT_TABLES (4) 109 #define MAX_MMAP_REGIONS (16) 110 111 #define CACHE_WRITEBACK_SHIFT (6) 112 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 113 114 /* Power states */ 115 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1) 116 #define PLAT_MAX_OFF_STATE 2 117 #define PLAT_MAX_RET_STATE 1 118 119 /* Interrupt controller */ 120 #define PLAT_ARM_GICD_BASE GICD_BASE 121 #define PLAT_ARM_GICC_BASE GICC_BASE 122 123 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 124 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 125 GIC_INTR_CFG_LEVEL), \ 126 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 127 GIC_INTR_CFG_LEVEL), \ 128 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 129 GIC_INTR_CFG_LEVEL), \ 130 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 131 GIC_INTR_CFG_LEVEL), \ 132 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133 GIC_INTR_CFG_LEVEL), \ 134 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_LEVEL), \ 136 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_LEVEL), \ 138 INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_LEVEL), \ 140 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_LEVEL), \ 142 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_LEVEL), \ 144 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_LEVEL), \ 146 INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 147 GIC_INTR_CFG_LEVEL), \ 148 INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \ 149 GIC_INTR_CFG_LEVEL) 150 151 #define PLAT_ARM_G0_IRQ_PROPS(grp) 152 153 #endif /* __PLATFORM_DEF_H__ */ 154