1e35d0edbSJorge Ramirez-Ortiz /* 20818e9e8SAntonio Nino Diaz * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3e35d0edbSJorge Ramirez-Ortiz * 4e35d0edbSJorge Ramirez-Ortiz * SPDX-License-Identifier: BSD-3-Clause 5e35d0edbSJorge Ramirez-Ortiz */ 6e35d0edbSJorge Ramirez-Ortiz 7*c3cf06f1SAntonio Nino Diaz #ifndef PLAT_PRIVATE_H 8*c3cf06f1SAntonio Nino Diaz #define PLAT_PRIVATE_H 9e35d0edbSJorge Ramirez-Ortiz 10e35d0edbSJorge Ramirez-Ortiz #include <bl_common.h> 11e35d0edbSJorge Ramirez-Ortiz #include "hi3798cv200.h" 12e35d0edbSJorge Ramirez-Ortiz 13e35d0edbSJorge Ramirez-Ortiz void plat_configure_mmu_el3(unsigned long total_base, 14e35d0edbSJorge Ramirez-Ortiz unsigned long total_size, 15e35d0edbSJorge Ramirez-Ortiz unsigned long ro_start, 16e35d0edbSJorge Ramirez-Ortiz unsigned long ro_limit, 17e35d0edbSJorge Ramirez-Ortiz unsigned long coh_start, 18e35d0edbSJorge Ramirez-Ortiz unsigned long coh_limit); 19e35d0edbSJorge Ramirez-Ortiz 20e35d0edbSJorge Ramirez-Ortiz void plat_configure_mmu_el1(unsigned long total_base, 21e35d0edbSJorge Ramirez-Ortiz unsigned long total_size, 22e35d0edbSJorge Ramirez-Ortiz unsigned long ro_start, 23e35d0edbSJorge Ramirez-Ortiz unsigned long ro_limit, 24e35d0edbSJorge Ramirez-Ortiz unsigned long coh_start, 25e35d0edbSJorge Ramirez-Ortiz unsigned long coh_limit); 26e35d0edbSJorge Ramirez-Ortiz 27e35d0edbSJorge Ramirez-Ortiz void plat_io_setup(void); 28e35d0edbSJorge Ramirez-Ortiz 290818e9e8SAntonio Nino Diaz unsigned int poplar_calc_core_pos(u_register_t mpidr); 300818e9e8SAntonio Nino Diaz 310818e9e8SAntonio Nino Diaz void poplar_gic_driver_init(void); 320818e9e8SAntonio Nino Diaz void poplar_gic_init(void); 330818e9e8SAntonio Nino Diaz void poplar_gic_cpuif_enable(void); 340818e9e8SAntonio Nino Diaz void poplar_gic_pcpu_init(void); 350818e9e8SAntonio Nino Diaz 36*c3cf06f1SAntonio Nino Diaz #endif /* PLAT_PRIVATE_H */ 37