1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_gic.h> 10 #include <assert.h> 11 #include <bl31.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <cortex_a53.h> 15 #include <debug.h> 16 #include <errno.h> 17 #include <generic_delay_timer.h> 18 #include <mmio.h> 19 #include <plat_arm.h> 20 #include <platform.h> 21 #include <stddef.h> 22 #include <string.h> 23 #include "hi3798cv200.h" 24 #include "plat_private.h" 25 #include "platform_def.h" 26 27 /* Memory ranges for code and RO data sections */ 28 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 29 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 30 31 /* Memory ranges for coherent memory section */ 32 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 33 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 34 35 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45) 36 37 static entry_point_info_t bl33_image_ep_info; 38 39 static void hisi_tzpc_sec_init(void) 40 { 41 mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE); 42 } 43 44 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 45 { 46 return &bl33_image_ep_info; 47 } 48 49 void bl31_early_platform_setup(bl31_params_t *from_bl2, 50 void *plat_params_from_bl2) 51 { 52 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 53 54 /* Init console for crash report */ 55 plat_crash_console_init(); 56 57 bl33_image_ep_info = *from_bl2->bl33_ep_info; 58 } 59 60 void bl31_platform_setup(void) 61 { 62 /* Init arch timer */ 63 generic_delay_timer_init(); 64 65 /* Init GIC distributor and CPU interface */ 66 plat_arm_gic_driver_init(); 67 plat_arm_gic_init(); 68 69 /* Init security properties of IP blocks */ 70 hisi_tzpc_sec_init(); 71 } 72 73 void bl31_plat_runtime_setup(void) 74 { 75 /* do nothing */ 76 } 77 78 void bl31_plat_arch_setup(void) 79 { 80 plat_configure_mmu_el3(BL31_RO_BASE, 81 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), 82 BL31_RO_BASE, 83 BL31_RO_LIMIT, 84 BL31_COHERENT_RAM_BASE, 85 BL31_COHERENT_RAM_LIMIT); 86 87 INFO("Boot BL33 from 0x%lx for %lu Bytes\n", 88 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); 89 } 90