1 /* 2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 #include <string.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <bl31/bl31.h> 19 #include <common/bl_common.h> 20 #include <common/debug.h> 21 #include <cortex_a53.h> 22 #include <drivers/arm/pl011.h> 23 #include <drivers/generic_delay_timer.h> 24 #include <lib/mmio.h> 25 #include <plat/common/platform.h> 26 27 #include "hi3798cv200.h" 28 #include "plat_private.h" 29 30 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45) 31 32 static entry_point_info_t bl32_image_ep_info; 33 static entry_point_info_t bl33_image_ep_info; 34 static console_t console; 35 36 static void hisi_tzpc_sec_init(void) 37 { 38 mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE); 39 } 40 41 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 42 { 43 entry_point_info_t *next_image_info; 44 45 assert(sec_state_is_valid(type)); 46 next_image_info = (type == NON_SECURE) 47 ? &bl33_image_ep_info : &bl32_image_ep_info; 48 /* 49 * None of the images on the ARM development platforms can have 0x0 50 * as the entrypoint 51 */ 52 if (next_image_info->pc) 53 return next_image_info; 54 else 55 return NULL; 56 } 57 58 /******************************************************************************* 59 * Perform any BL31 early platform setup common to ARM standard platforms. 60 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 61 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 62 * done before the MMU is initialized so that the memory layout can be used 63 * while creating page tables. BL2 has flushed this information to memory, so 64 * we are guaranteed to pick up good data. 65 ******************************************************************************/ 66 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 67 u_register_t arg2, u_register_t arg3) 68 { 69 void *from_bl2; 70 71 from_bl2 = (void *) arg0; 72 73 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, 74 PL011_BAUDRATE, &console); 75 76 /* Init console for crash report */ 77 plat_crash_console_init(); 78 79 /* 80 * Check params passed from BL2 should not be NULL, 81 */ 82 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 83 84 assert(params_from_bl2 != NULL); 85 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 86 assert(params_from_bl2->h.version >= VERSION_2); 87 88 bl_params_node_t *bl_params = params_from_bl2->head; 89 90 /* 91 * Copy BL33 and BL32 (if present), entry point information. 92 * They are stored in Secure RAM, in BL2's address space. 93 */ 94 while (bl_params) { 95 if (bl_params->image_id == BL32_IMAGE_ID) 96 bl32_image_ep_info = *bl_params->ep_info; 97 98 if (bl_params->image_id == BL33_IMAGE_ID) 99 bl33_image_ep_info = *bl_params->ep_info; 100 101 bl_params = bl_params->next_params_info; 102 } 103 104 if (bl33_image_ep_info.pc == 0) 105 panic(); 106 } 107 108 void bl31_platform_setup(void) 109 { 110 /* Init arch timer */ 111 generic_delay_timer_init(); 112 113 /* Init GIC distributor and CPU interface */ 114 poplar_gic_driver_init(); 115 poplar_gic_init(); 116 117 /* Init security properties of IP blocks */ 118 hisi_tzpc_sec_init(); 119 } 120 121 void bl31_plat_arch_setup(void) 122 { 123 plat_configure_mmu_el3(BL31_BASE, 124 (BL31_LIMIT - BL31_BASE), 125 BL_CODE_BASE, 126 BL_CODE_END, 127 BL_COHERENT_RAM_BASE, 128 BL_COHERENT_RAM_END); 129 130 INFO("Boot BL33 from 0x%lx for %" PRIu64 " Bytes\n", 131 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); 132 } 133