1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_gic.h> 10 #include <assert.h> 11 #include <bl31.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <cortex_a53.h> 15 #include <debug.h> 16 #include <errno.h> 17 #include <generic_delay_timer.h> 18 #include <mmio.h> 19 #include <plat_arm.h> 20 #include <platform.h> 21 #include <stddef.h> 22 #include <string.h> 23 #include "hi3798cv200.h" 24 #include "plat_private.h" 25 #include "platform_def.h" 26 27 /* Memory ranges for code and RO data sections */ 28 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 29 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 30 31 /* Memory ranges for coherent memory section */ 32 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 33 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 34 35 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45) 36 37 static entry_point_info_t bl32_image_ep_info; 38 static entry_point_info_t bl33_image_ep_info; 39 40 static void hisi_tzpc_sec_init(void) 41 { 42 mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE); 43 } 44 45 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 46 { 47 entry_point_info_t *next_image_info; 48 49 assert(sec_state_is_valid(type)); 50 next_image_info = (type == NON_SECURE) 51 ? &bl33_image_ep_info : &bl32_image_ep_info; 52 /* 53 * None of the images on the ARM development platforms can have 0x0 54 * as the entrypoint 55 */ 56 if (next_image_info->pc) 57 return next_image_info; 58 else 59 return NULL; 60 } 61 62 void bl31_early_platform_setup(bl31_params_t *from_bl2, 63 void *plat_params_from_bl2) 64 { 65 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 66 67 /* Init console for crash report */ 68 plat_crash_console_init(); 69 70 71 /* 72 * Copy BL32 (if populated by BL2) and BL33 entry point information. 73 * They are stored in Secure RAM, in BL2's address space. 74 */ 75 if (from_bl2->bl32_ep_info) 76 bl32_image_ep_info = *from_bl2->bl32_ep_info; 77 bl33_image_ep_info = *from_bl2->bl33_ep_info; 78 } 79 80 void bl31_platform_setup(void) 81 { 82 /* Init arch timer */ 83 generic_delay_timer_init(); 84 85 /* Init GIC distributor and CPU interface */ 86 plat_arm_gic_driver_init(); 87 plat_arm_gic_init(); 88 89 /* Init security properties of IP blocks */ 90 hisi_tzpc_sec_init(); 91 } 92 93 void bl31_plat_runtime_setup(void) 94 { 95 /* do nothing */ 96 } 97 98 void bl31_plat_arch_setup(void) 99 { 100 plat_configure_mmu_el3(BL31_RO_BASE, 101 (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), 102 BL31_RO_BASE, 103 BL31_RO_LIMIT, 104 BL31_COHERENT_RAM_BASE, 105 BL31_COHERENT_RAM_LIMIT); 106 107 INFO("Boot BL33 from 0x%lx for %lu Bytes\n", 108 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); 109 } 110