1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <arm_gic.h> 10 #include <assert.h> 11 #include <bl31.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <cortex_a53.h> 15 #include <debug.h> 16 #include <errno.h> 17 #include <generic_delay_timer.h> 18 #include <mmio.h> 19 #include <plat_arm.h> 20 #include <platform.h> 21 #include <stddef.h> 22 #include <string.h> 23 #include "hi3798cv200.h" 24 #include "plat_private.h" 25 #include "platform_def.h" 26 27 /* Memory ranges for code and RO data sections */ 28 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 29 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 30 31 /* Memory ranges for coherent memory section */ 32 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 33 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 34 35 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45) 36 37 static entry_point_info_t bl32_image_ep_info; 38 static entry_point_info_t bl33_image_ep_info; 39 40 static void hisi_tzpc_sec_init(void) 41 { 42 mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE); 43 } 44 45 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 46 { 47 entry_point_info_t *next_image_info; 48 49 assert(sec_state_is_valid(type)); 50 next_image_info = (type == NON_SECURE) 51 ? &bl33_image_ep_info : &bl32_image_ep_info; 52 /* 53 * None of the images on the ARM development platforms can have 0x0 54 * as the entrypoint 55 */ 56 if (next_image_info->pc) 57 return next_image_info; 58 else 59 return NULL; 60 } 61 62 /******************************************************************************* 63 * Perform any BL31 early platform setup common to ARM standard platforms. 64 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 65 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be 66 * done before the MMU is initialized so that the memory layout can be used 67 * while creating page tables. BL2 has flushed this information to memory, so 68 * we are guaranteed to pick up good data. 69 ******************************************************************************/ 70 #if LOAD_IMAGE_V2 71 void bl31_early_platform_setup(void *from_bl2, 72 void *plat_params_from_bl2) 73 #else 74 void bl31_early_platform_setup(bl31_params_t *from_bl2, 75 void *plat_params_from_bl2) 76 #endif 77 { 78 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 79 80 /* Init console for crash report */ 81 plat_crash_console_init(); 82 83 #if LOAD_IMAGE_V2 84 /* 85 * Check params passed from BL2 should not be NULL, 86 */ 87 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 88 89 assert(params_from_bl2 != NULL); 90 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 91 assert(params_from_bl2->h.version >= VERSION_2); 92 93 bl_params_node_t *bl_params = params_from_bl2->head; 94 95 /* 96 * Copy BL33 and BL32 (if present), entry point information. 97 * They are stored in Secure RAM, in BL2's address space. 98 */ 99 while (bl_params) { 100 if (bl_params->image_id == BL32_IMAGE_ID) 101 bl32_image_ep_info = *bl_params->ep_info; 102 103 if (bl_params->image_id == BL33_IMAGE_ID) 104 bl33_image_ep_info = *bl_params->ep_info; 105 106 bl_params = bl_params->next_params_info; 107 } 108 109 if (bl33_image_ep_info.pc == 0) 110 panic(); 111 112 #else /* LOAD_IMAGE_V2 */ 113 114 /* 115 * Check params passed from BL2 should not be NULL, 116 */ 117 assert(params_from_bl2 != NULL); 118 assert(params_from_bl2->h.type == PARAM_BL31); 119 assert(params_from_bl2->h.version >= VERSION_1); 120 121 /* 122 * Copy BL32 (if populated by BL2) and BL33 entry point information. 123 * They are stored in Secure RAM, in BL2's address space. 124 */ 125 if (from_bl2->bl32_ep_info) 126 bl32_image_ep_info = *from_bl2->bl32_ep_info; 127 bl33_image_ep_info = *from_bl2->bl33_ep_info; 128 #endif /* LOAD_IMAGE_V2 */ 129 } 130 131 void bl31_platform_setup(void) 132 { 133 /* Init arch timer */ 134 generic_delay_timer_init(); 135 136 /* Init GIC distributor and CPU interface */ 137 plat_arm_gic_driver_init(); 138 plat_arm_gic_init(); 139 140 /* Init security properties of IP blocks */ 141 hisi_tzpc_sec_init(); 142 } 143 144 void bl31_plat_runtime_setup(void) 145 { 146 /* do nothing */ 147 } 148 149 void bl31_plat_arch_setup(void) 150 { 151 plat_configure_mmu_el3(BL31_BASE, 152 (BL31_LIMIT - BL31_BASE), 153 BL31_RO_BASE, 154 BL31_RO_LIMIT, 155 BL31_COHERENT_RAM_BASE, 156 BL31_COHERENT_RAM_LIMIT); 157 158 INFO("Boot BL33 from 0x%lx for %lu Bytes\n", 159 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); 160 } 161