1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/arm/pl011.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/partition/partition.h> 18 #include <drivers/synopsys/dw_mmc.h> 19 #include <drivers/mmc.h> 20 #include <lib/mmio.h> 21 #include <lib/optee_utils.h> 22 #include <plat/common/platform.h> 23 24 #include "hi3798cv200.h" 25 #include "plat_private.h" 26 27 /* Memory ranges for code and read only data sections */ 28 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 29 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 30 31 /* Memory ranges for coherent memory section */ 32 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 33 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 34 35 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 36 static console_pl011_t console; 37 38 /******************************************************************************* 39 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 40 * Return 0 on success, -1 otherwise. 41 ******************************************************************************/ 42 int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 43 { 44 /* 45 * This platform has no SCP_BL2 yet 46 */ 47 return 0; 48 } 49 50 /******************************************************************************* 51 * Gets SPSR for BL32 entry 52 ******************************************************************************/ 53 uint32_t poplar_get_spsr_for_bl32_entry(void) 54 { 55 /* 56 * The Secure Payload Dispatcher service is responsible for 57 * setting the SPSR prior to entry into the BL3-2 image. 58 */ 59 return 0; 60 } 61 62 /******************************************************************************* 63 * Gets SPSR for BL33 entry 64 ******************************************************************************/ 65 #ifndef AARCH32 66 uint32_t poplar_get_spsr_for_bl33_entry(void) 67 { 68 unsigned long el_status; 69 unsigned int mode; 70 uint32_t spsr; 71 72 /* Figure out what mode we enter the non-secure world in */ 73 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 74 el_status &= ID_AA64PFR0_ELX_MASK; 75 76 mode = (el_status) ? MODE_EL2 : MODE_EL1; 77 78 /* 79 * TODO: Consider the possibility of specifying the SPSR in 80 * the FIP ToC and allowing the platform to have a say as 81 * well. 82 */ 83 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 84 return spsr; 85 } 86 #else 87 uint32_t poplar_get_spsr_for_bl33_entry(void) 88 { 89 unsigned int hyp_status, mode, spsr; 90 91 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 92 93 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 94 95 /* 96 * TODO: Consider the possibility of specifying the SPSR in 97 * the FIP ToC and allowing the platform to have a say as 98 * well. 99 */ 100 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 101 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 102 return spsr; 103 } 104 #endif /* AARCH32 */ 105 106 int poplar_bl2_handle_post_image_load(unsigned int image_id) 107 { 108 int err = 0; 109 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 110 #ifdef SPD_opteed 111 bl_mem_params_node_t *pager_mem_params = NULL; 112 bl_mem_params_node_t *paged_mem_params = NULL; 113 #endif 114 115 assert(bl_mem_params); 116 117 switch (image_id) { 118 #ifdef AARCH64 119 case BL32_IMAGE_ID: 120 #ifdef SPD_opteed 121 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 122 assert(pager_mem_params); 123 124 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 125 assert(paged_mem_params); 126 127 err = parse_optee_header(&bl_mem_params->ep_info, 128 &pager_mem_params->image_info, 129 &paged_mem_params->image_info); 130 if (err != 0) { 131 WARN("OPTEE header parse error.\n"); 132 } 133 134 /* 135 * OP-TEE expect to receive DTB address in x2. 136 * This will be copied into x2 by dispatcher. 137 * Set this (arg3) if necessary 138 */ 139 /* bl_mem_params->ep_info.args.arg3 = PLAT_HIKEY_DT_BASE; */ 140 #endif 141 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); 142 break; 143 #endif 144 145 case BL33_IMAGE_ID: 146 /* BL33 expects to receive the primary CPU MPID (through r0) */ 147 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 148 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); 149 break; 150 151 #ifdef SCP_BL2_BASE 152 case SCP_BL2_IMAGE_ID: 153 /* The subsequent handling of SCP_BL2 is platform specific */ 154 err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info); 155 if (err) { 156 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 157 } 158 break; 159 #endif 160 default: 161 /* Do nothing in default case */ 162 break; 163 } 164 165 return err; 166 } 167 168 /******************************************************************************* 169 * This function can be used by the platforms to update/use image 170 * information for given `image_id`. 171 ******************************************************************************/ 172 int bl2_plat_handle_post_image_load(unsigned int image_id) 173 { 174 return poplar_bl2_handle_post_image_load(image_id); 175 } 176 177 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, 178 u_register_t arg2, u_register_t arg3) 179 { 180 struct meminfo *mem_layout = (struct meminfo *)arg1; 181 #if !POPLAR_RECOVERY 182 struct mmc_device_info info; 183 184 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 185 #endif 186 187 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, 188 PL011_BAUDRATE, &console); 189 190 /* Enable arch timer */ 191 generic_delay_timer_init(); 192 193 bl2_tzram_layout = *mem_layout; 194 195 #if !POPLAR_RECOVERY 196 /* SoC-specific emmc register are initialized/configured by bootrom */ 197 INFO("BL2: initializing emmc\n"); 198 info.mmc_dev_type = MMC_IS_EMMC; 199 dw_mmc_init(¶ms, &info); 200 #endif 201 202 plat_io_setup(); 203 } 204 205 void bl2_plat_arch_setup(void) 206 { 207 plat_configure_mmu_el1(bl2_tzram_layout.total_base, 208 bl2_tzram_layout.total_size, 209 BL2_RO_BASE, 210 BL2_RO_LIMIT, 211 BL2_COHERENT_RAM_BASE, 212 BL2_COHERENT_RAM_LIMIT); 213 } 214 215 void bl2_platform_setup(void) 216 { 217 } 218 219 uintptr_t plat_get_ns_image_entrypoint(void) 220 { 221 #ifdef PRELOADED_BL33_BASE 222 return PRELOADED_BL33_BASE; 223 #else 224 return PLAT_POPLAR_NS_IMAGE_OFFSET; 225 #endif 226 } 227