1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <dw_mmc.h> 14 #include <emmc.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <mmio.h> 18 #include <partition/partition.h> 19 #include <platform.h> 20 #include <string.h> 21 #include "hi3798cv200.h" 22 #include "plat_private.h" 23 24 /* Memory ranges for code and read only data sections */ 25 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 26 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 27 28 /* Memory ranges for coherent memory section */ 29 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 30 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 31 32 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 33 34 #if !LOAD_IMAGE_V2 35 36 /******************************************************************************* 37 * This structure represents the superset of information that is passed to 38 * BL31, e.g. while passing control to it from BL2, bl31_params 39 * and other platform specific params 40 ******************************************************************************/ 41 typedef struct bl2_to_bl31_params_mem { 42 bl31_params_t bl31_params; 43 image_info_t bl31_image_info; 44 image_info_t bl32_image_info; 45 image_info_t bl33_image_info; 46 entry_point_info_t bl33_ep_info; 47 entry_point_info_t bl32_ep_info; 48 entry_point_info_t bl31_ep_info; 49 } bl2_to_bl31_params_mem_t; 50 51 static bl2_to_bl31_params_mem_t bl31_params_mem; 52 53 meminfo_t *bl2_plat_sec_mem_layout(void) 54 { 55 return &bl2_tzram_layout; 56 } 57 58 #ifdef SCP_BL2_BASE 59 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 60 { 61 /* 62 * This platform has no SCP_BL2 yet 63 */ 64 } 65 #endif 66 #endif /* LOAD_IMAGE_V2 */ 67 68 /******************************************************************************* 69 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 70 * Return 0 on success, -1 otherwise. 71 ******************************************************************************/ 72 #if LOAD_IMAGE_V2 73 int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 74 #else 75 int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) 76 #endif 77 { 78 /* 79 * This platform has no SCP_BL2 yet 80 */ 81 return 0; 82 } 83 84 /******************************************************************************* 85 * Gets SPSR for BL32 entry 86 ******************************************************************************/ 87 uint32_t poplar_get_spsr_for_bl32_entry(void) 88 { 89 /* 90 * The Secure Payload Dispatcher service is responsible for 91 * setting the SPSR prior to entry into the BL3-2 image. 92 */ 93 return 0; 94 } 95 96 /******************************************************************************* 97 * Gets SPSR for BL33 entry 98 ******************************************************************************/ 99 #ifndef AARCH32 100 uint32_t poplar_get_spsr_for_bl33_entry(void) 101 { 102 unsigned long el_status; 103 unsigned int mode; 104 uint32_t spsr; 105 106 /* Figure out what mode we enter the non-secure world in */ 107 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 108 el_status &= ID_AA64PFR0_ELX_MASK; 109 110 mode = (el_status) ? MODE_EL2 : MODE_EL1; 111 112 /* 113 * TODO: Consider the possibility of specifying the SPSR in 114 * the FIP ToC and allowing the platform to have a say as 115 * well. 116 */ 117 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 118 return spsr; 119 } 120 #else 121 uint32_t poplar_get_spsr_for_bl33_entry(void) 122 { 123 unsigned int hyp_status, mode, spsr; 124 125 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 126 127 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 128 129 /* 130 * TODO: Consider the possibility of specifying the SPSR in 131 * the FIP ToC and allowing the platform to have a say as 132 * well. 133 */ 134 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 135 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 136 return spsr; 137 } 138 #endif /* AARCH32 */ 139 140 #if LOAD_IMAGE_V2 141 int poplar_bl2_handle_post_image_load(unsigned int image_id) 142 { 143 int err = 0; 144 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 145 146 assert(bl_mem_params); 147 148 switch (image_id) { 149 #ifdef AARCH64 150 case BL32_IMAGE_ID: 151 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); 152 break; 153 #endif 154 155 case BL33_IMAGE_ID: 156 /* BL33 expects to receive the primary CPU MPID (through r0) */ 157 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 158 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); 159 break; 160 161 #ifdef SCP_BL2_BASE 162 case SCP_BL2_IMAGE_ID: 163 /* The subsequent handling of SCP_BL2 is platform specific */ 164 err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info); 165 if (err) { 166 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 167 } 168 break; 169 #endif 170 } 171 172 return err; 173 } 174 175 /******************************************************************************* 176 * This function can be used by the platforms to update/use image 177 * information for given `image_id`. 178 ******************************************************************************/ 179 int bl2_plat_handle_post_image_load(unsigned int image_id) 180 { 181 return poplar_bl2_handle_post_image_load(image_id); 182 } 183 184 #else /* LOAD_IMAGE_V2 */ 185 186 bl31_params_t *bl2_plat_get_bl31_params(void) 187 { 188 bl31_params_t *bl2_to_bl31_params = NULL; 189 190 /* 191 * Initialise the memory for all the arguments that needs to 192 * be passed to BL3-1 193 */ 194 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 195 196 /* Assign memory for TF related information */ 197 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 198 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 199 200 /* Fill BL3-1 related information */ 201 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 202 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, 203 PARAM_IMAGE_BINARY, VERSION_1, 0); 204 205 /* Fill BL3-2 related information if it exists */ 206 #ifdef BL32_BASE 207 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 208 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 209 VERSION_1, 0); 210 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 211 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 212 VERSION_1, 0); 213 #endif 214 215 /* Fill BL3-3 related information */ 216 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 217 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 218 PARAM_EP, VERSION_1, 0); 219 220 /* BL3-3 expects to receive the primary CPU MPID (through x0) */ 221 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 222 223 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 224 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, 225 PARAM_IMAGE_BINARY, VERSION_1, 0); 226 227 return bl2_to_bl31_params; 228 } 229 230 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 231 { 232 #if DEBUG 233 bl31_params_mem.bl31_ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL; 234 #endif 235 236 return &bl31_params_mem.bl31_ep_info; 237 } 238 239 void bl2_plat_set_bl31_ep_info(image_info_t *image, 240 entry_point_info_t *bl31_ep_info) 241 { 242 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 243 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 244 DISABLE_ALL_EXCEPTIONS); 245 } 246 247 /******************************************************************************* 248 * Before calling this function BL32 is loaded in memory and its entrypoint 249 * is set by load_image. This is a placeholder for the platform to change 250 * the entrypoint of BL32 and set SPSR and security state. 251 * On Poplar we only set the security state of the entrypoint 252 ******************************************************************************/ 253 #ifdef BL32_BASE 254 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 255 entry_point_info_t *bl32_ep_info) 256 { 257 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 258 /* 259 * The Secure Payload Dispatcher service is responsible for 260 * setting the SPSR prior to entry into the BL32 image. 261 */ 262 bl32_ep_info->spsr = 0; 263 } 264 265 /******************************************************************************* 266 * Populate the extents of memory available for loading BL32 267 ******************************************************************************/ 268 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 269 { 270 /* 271 * Populate the extents of memory available for loading BL32. 272 */ 273 bl32_meminfo->total_base = BL32_BASE; 274 bl32_meminfo->free_base = BL32_BASE; 275 bl32_meminfo->total_size = 276 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 277 bl32_meminfo->free_size = 278 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 279 } 280 #endif /* BL32_BASE */ 281 282 void bl2_plat_set_bl33_ep_info(image_info_t *image, 283 entry_point_info_t *bl33_ep_info) 284 { 285 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 286 bl33_ep_info->spsr = poplar_get_spsr_for_bl33_entry(); 287 bl33_ep_info->args.arg2 = image->image_size; 288 } 289 290 void bl2_plat_flush_bl31_params(void) 291 { 292 flush_dcache_range((unsigned long)&bl31_params_mem, 293 sizeof(bl2_to_bl31_params_mem_t)); 294 } 295 296 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 297 { 298 bl33_meminfo->total_base = DDR_BASE; 299 bl33_meminfo->total_size = DDR_SIZE; 300 bl33_meminfo->free_base = DDR_BASE; 301 bl33_meminfo->free_size = DDR_SIZE; 302 } 303 #endif /* LOAD_IMAGE_V2 */ 304 305 void bl2_early_platform_setup(meminfo_t *mem_layout) 306 { 307 #if !POPLAR_RECOVERY 308 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 309 #endif 310 311 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 312 313 /* Enable arch timer */ 314 generic_delay_timer_init(); 315 316 bl2_tzram_layout = *mem_layout; 317 318 #if !POPLAR_RECOVERY 319 /* SoC-specific emmc register are initialized/configured by bootrom */ 320 INFO("BL2: initializing emmc\n"); 321 dw_mmc_init(¶ms); 322 #endif 323 324 plat_io_setup(); 325 } 326 327 void bl2_plat_arch_setup(void) 328 { 329 plat_configure_mmu_el1(bl2_tzram_layout.total_base, 330 bl2_tzram_layout.total_size, 331 BL2_RO_BASE, 332 BL2_RO_LIMIT, 333 BL2_COHERENT_RAM_BASE, 334 BL2_COHERENT_RAM_LIMIT); 335 } 336 337 void bl2_platform_setup(void) 338 { 339 } 340 341 uintptr_t plat_get_ns_image_entrypoint(void) 342 { 343 #ifdef PRELOADED_BL33_BASE 344 return PRELOADED_BL33_BASE; 345 #else 346 return PLAT_POPLAR_NS_IMAGE_OFFSET; 347 #endif 348 } 349