1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <emmc.h> 14 #include <errno.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <pl061_gpio.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <tbbr_img_def.h> 22 #include "../../bl1/bl1_private.h" 23 #include "hi3798cv200.h" 24 #include "plat_private.h" 25 26 /* Symbols from link script for conherent section */ 27 extern unsigned long __COHERENT_RAM_START__; 28 extern unsigned long __COHERENT_RAM_END__; 29 30 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 31 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 32 33 /* Data structure which holds the extents of the trusted RAM for BL1 */ 34 static meminfo_t bl1_tzram_layout; 35 36 meminfo_t *bl1_plat_sec_mem_layout(void) 37 { 38 return &bl1_tzram_layout; 39 } 40 41 #if LOAD_IMAGE_V2 42 /******************************************************************************* 43 * Function that takes a memory layout into which BL2 has been loaded and 44 * populates a new memory layout for BL2 that ensures that BL1's data sections 45 * resident in secure RAM are not visible to BL2. 46 ******************************************************************************/ 47 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 48 meminfo_t *bl2_mem_layout) 49 { 50 51 assert(bl1_mem_layout != NULL); 52 assert(bl2_mem_layout != NULL); 53 54 /* 55 * Cannot use default weak implementation in bl1main.c because 56 * BL1 RW data is not at the top of bl1_mem_layout 57 */ 58 bl2_mem_layout->total_base = BL2_BASE; 59 bl2_mem_layout->total_size = BL32_LIMIT - BL2_BASE; 60 61 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 62 } 63 #endif /* LOAD_IMAGE_V2 */ 64 65 void bl1_early_platform_setup(void) 66 { 67 /* Initialize the console to provide early debug support */ 68 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 69 70 /* Allow BL1 to see the whole Trusted RAM */ 71 bl1_tzram_layout.total_base = BL1_RW_BASE; 72 bl1_tzram_layout.total_size = BL1_RW_SIZE; 73 74 #if !LOAD_IMAGE_V2 75 /* Calculate how much RAM BL1 is using and how much remains free */ 76 bl1_tzram_layout.free_base = BL1_RW_BASE; 77 bl1_tzram_layout.free_size = BL1_RW_SIZE; 78 79 reserve_mem(&bl1_tzram_layout.free_base, 80 &bl1_tzram_layout.free_size, 81 BL1_RAM_BASE, 82 BL1_RAM_LIMIT - BL1_RAM_BASE); 83 #endif 84 85 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 86 BL1_RAM_LIMIT - BL1_RAM_BASE); 87 } 88 89 void bl1_plat_arch_setup(void) 90 { 91 plat_configure_mmu_el3(bl1_tzram_layout.total_base, 92 bl1_tzram_layout.total_size, 93 BL1_RO_BASE, /* l-loader and BL1 ROM */ 94 BL1_RO_LIMIT, 95 BL1_COHERENT_RAM_BASE, 96 BL1_COHERENT_RAM_LIMIT); 97 } 98 99 void bl1_platform_setup(void) 100 { 101 int i; 102 #if !POPLAR_RECOVERY 103 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 104 #endif 105 106 generic_delay_timer_init(); 107 108 pl061_gpio_init(); 109 for (i = 0; i < GPIO_MAX; i++) 110 pl061_gpio_register(GPIO_BASE(i), i); 111 112 #if !POPLAR_RECOVERY 113 /* SoC-specific emmc register are initialized/configured by bootrom */ 114 INFO("BL1: initializing emmc\n"); 115 dw_mmc_init(¶ms); 116 #endif 117 118 plat_io_setup(); 119 } 120 121 unsigned int bl1_plat_get_next_image_id(void) 122 { 123 return BL2_IMAGE_ID; 124 } 125