1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <errno.h> 14 #include <generic_delay_timer.h> 15 #include <mmc.h> 16 #include <mmio.h> 17 #include <pl061_gpio.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <tbbr_img_def.h> 22 #include "../../bl1/bl1_private.h" 23 #include "hi3798cv200.h" 24 #include "plat_private.h" 25 26 /* Data structure which holds the extents of the trusted RAM for BL1 */ 27 static meminfo_t bl1_tzram_layout; 28 static meminfo_t bl2_tzram_layout; 29 30 /* 31 * Cannot use default weak implementation in bl1_main.c because BL1 RW data is 32 * not at the top of the secure memory. 33 */ 34 int bl1_plat_handle_post_image_load(unsigned int image_id) 35 { 36 image_desc_t *image_desc; 37 entry_point_info_t *ep_info; 38 39 if (image_id != BL2_IMAGE_ID) 40 return 0; 41 42 /* Get the image descriptor */ 43 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 44 assert(image_desc != NULL); 45 46 /* Get the entry point info */ 47 ep_info = &image_desc->ep_info; 48 49 bl2_tzram_layout.total_base = BL2_BASE; 50 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; 51 52 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); 53 54 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout; 55 56 VERBOSE("BL1: BL2 memory layout address = %p\n", 57 (void *)&bl2_tzram_layout); 58 59 return 0; 60 } 61 62 void bl1_early_platform_setup(void) 63 { 64 /* Initialize the console to provide early debug support */ 65 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 66 67 /* Allow BL1 to see the whole Trusted RAM */ 68 bl1_tzram_layout.total_base = BL1_RW_BASE; 69 bl1_tzram_layout.total_size = BL1_RW_SIZE; 70 71 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 72 BL1_RAM_LIMIT - BL1_RAM_BASE); 73 } 74 75 void bl1_plat_arch_setup(void) 76 { 77 plat_configure_mmu_el3(bl1_tzram_layout.total_base, 78 bl1_tzram_layout.total_size, 79 BL1_RO_BASE, /* l-loader and BL1 ROM */ 80 BL1_RO_LIMIT, 81 BL_COHERENT_RAM_BASE, 82 BL_COHERENT_RAM_END); 83 } 84 85 void bl1_platform_setup(void) 86 { 87 int i; 88 #if !POPLAR_RECOVERY 89 struct mmc_device_info info; 90 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 91 #endif 92 93 generic_delay_timer_init(); 94 95 pl061_gpio_init(); 96 for (i = 0; i < GPIO_MAX; i++) 97 pl061_gpio_register(GPIO_BASE(i), i); 98 99 #if !POPLAR_RECOVERY 100 /* SoC-specific emmc register are initialized/configured by bootrom */ 101 INFO("BL1: initializing emmc\n"); 102 info.mmc_dev_type = MMC_IS_EMMC; 103 dw_mmc_init(¶ms, &info); 104 #endif 105 106 plat_io_setup(); 107 } 108 109 unsigned int bl1_plat_get_next_image_id(void) 110 { 111 return BL2_IMAGE_ID; 112 } 113