1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../hikey960_def.h" 12 13 14 /* 15 * Generic platform constants 16 */ 17 18 /* Size of cacheable stacks */ 19 #define PLATFORM_STACK_SIZE 0x800 20 21 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 22 23 #define PLATFORM_CACHE_LINE_SIZE 64 24 #define PLATFORM_CLUSTER_COUNT 2 25 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 26 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 27 PLATFORM_CORE_COUNT_PER_CLUSTER) 28 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 29 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 30 PLATFORM_CLUSTER_COUNT + 1) 31 32 #define PLAT_MAX_RET_STATE 1 33 #define PLAT_MAX_OFF_STATE 2 34 35 #define MAX_IO_DEVICES 3 36 #define MAX_IO_HANDLES 4 37 /* UFS RPMB and UFS User Data */ 38 #define MAX_IO_BLOCK_DEVICES 2 39 40 41 /* 42 * Platform memory map related constants 43 */ 44 45 /* 46 * BL1 specific defines. 47 */ 48 #define BL1_RO_BASE (0x1AC00000) 49 #define BL1_RO_LIMIT (BL1_RO_BASE + 0x10000) 50 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC1_0000 */ 51 #define BL1_RW_SIZE (0x00188000) 52 #define BL1_RW_LIMIT (0x1B000000) 53 54 /* 55 * BL2 specific defines. 56 */ 57 #define BL2_BASE (BL1_RW_BASE + 0x8000) /* 1AC1_8000 */ 58 #define BL2_LIMIT (BL2_BASE + 0x40000) /* 1AC5_8000 */ 59 60 /* 61 * BL31 specific defines. 62 */ 63 #define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */ 64 #define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */ 65 66 /* 67 * BL3-2 specific defines. 68 */ 69 70 /* 71 * The TSP currently executes from TZC secured area of DRAM. 72 */ 73 #define BL32_DRAM_BASE DDR_SEC_BASE 74 #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 75 76 #if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID) 77 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 78 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 79 #define BL32_BASE BL32_DRAM_BASE 80 #define BL32_LIMIT BL32_DRAM_LIMIT 81 #elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID) 82 #error "SRAM storage of TSP payload is currently unsupported" 83 #else 84 #error "Currently unsupported HIKEY960_TSP_LOCATION_ID value" 85 #endif 86 87 #define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */ 88 #define NS_BL1U_SIZE (0x00100000) 89 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 90 91 #define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */ 92 #define HIKEY960_NS_TMP_OFFSET (0x1AE00000) 93 94 #define SCP_BL2_BASE BL31_BASE /* 1AC5_8000 */ 95 96 #define SCP_MEM_BASE (0x89C80000) 97 #define SCP_MEM_SIZE (0x00040000) 98 99 /* 100 * Platform specific page table and MMU setup constants 101 */ 102 #define ADDR_SPACE_SIZE (1ull << 32) 103 104 #if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 || IMAGE_BL32 105 #define MAX_XLAT_TABLES 3 106 #endif 107 108 #define MAX_MMAP_REGIONS 16 109 110 /* 111 * Declarations and constants to access the mailboxes safely. Each mailbox is 112 * aligned on the biggest cache line size in the platform. This is known only 113 * to the platform as it might have a combination of integrated and external 114 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 115 * line at any cache level. They could belong to different cpus/clusters & 116 * get written while being protected by different locks causing corruption of 117 * a valid mailbox address. 118 */ 119 #define CACHE_WRITEBACK_SHIFT 6 120 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 121 122 #endif /* __PLATFORM_DEF_H__ */ 123