1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../hikey960_def.h" 12 13 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 14 #define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 15 16 /* 17 * Generic platform constants 18 */ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE 0x800 22 23 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 24 25 #define PLATFORM_CACHE_LINE_SIZE 64 26 #define PLATFORM_CLUSTER_COUNT 2 27 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 28 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 29 PLATFORM_CORE_COUNT_PER_CLUSTER) 30 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 31 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 32 PLATFORM_CLUSTER_COUNT + 1) 33 34 #define PLAT_MAX_RUN_STATE 0 35 #define PLAT_MAX_STB_STATE 1 36 #define PLAT_MAX_RET_STATE 2 37 #define PLAT_MAX_OFF_STATE 3 38 39 #define MAX_IO_DEVICES 3 40 #define MAX_IO_HANDLES 4 41 /* UFS RPMB and UFS User Data */ 42 #define MAX_IO_BLOCK_DEVICES 2 43 44 45 /* 46 * Platform memory map related constants 47 */ 48 49 /* 50 * BL1 specific defines. 51 */ 52 #define BL1_RO_BASE (0x1AC00000) 53 #define BL1_RO_LIMIT (BL1_RO_BASE + 0x10000) 54 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC1_0000 */ 55 #define BL1_RW_SIZE (0x00188000) 56 #define BL1_RW_LIMIT (0x1B000000) 57 58 /* 59 * BL2 specific defines. 60 */ 61 #define BL2_BASE (BL1_RW_BASE + 0x8000) /* 1AC1_8000 */ 62 #define BL2_LIMIT (BL2_BASE + 0x40000) /* 1AC5_8000 */ 63 64 /* 65 * BL31 specific defines. 66 */ 67 #define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */ 68 #define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */ 69 70 /* 71 * BL3-2 specific defines. 72 */ 73 74 /* 75 * The TSP currently executes from TZC secured area of DRAM. 76 */ 77 #define BL32_DRAM_BASE DDR_SEC_BASE 78 #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 79 80 #if LOAD_IMAGE_V2 81 #ifdef SPD_opteed 82 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 83 #define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ 84 #define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 85 #endif 86 #endif 87 88 #if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID) 89 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 90 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 91 #define BL32_BASE BL32_DRAM_BASE 92 #define BL32_LIMIT BL32_DRAM_LIMIT 93 #elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID) 94 #error "SRAM storage of TSP payload is currently unsupported" 95 #else 96 #error "Currently unsupported HIKEY960_TSP_LOCATION_ID value" 97 #endif 98 99 /* BL32 is mandatory in AArch32 */ 100 #ifndef AARCH32 101 #ifdef SPD_none 102 #undef BL32_BASE 103 #endif /* SPD_none */ 104 #endif 105 106 #define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */ 107 #define NS_BL1U_SIZE (0x00100000) 108 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 109 110 #define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */ 111 #define HIKEY960_NS_TMP_OFFSET (0x1AE00000) 112 113 #define SCP_BL2_BASE (0x89C80000) 114 #define SCP_BL2_SIZE (0x00040000) 115 116 /* 117 * Platform specific page table and MMU setup constants 118 */ 119 #define ADDR_SPACE_SIZE (1ull << 32) 120 121 #if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32) 122 #define MAX_XLAT_TABLES 3 123 #endif 124 125 #ifdef IMAGE_BL2 126 #if LOAD_IMAGE_V2 127 #ifdef SPD_opteed 128 #define MAX_XLAT_TABLES 4 129 #else 130 #define MAX_XLAT_TABLES 3 131 #endif 132 #else 133 #define MAX_XLAT_TABLES 3 134 #endif 135 #endif 136 137 #define MAX_MMAP_REGIONS 16 138 139 /* 140 * Declarations and constants to access the mailboxes safely. Each mailbox is 141 * aligned on the biggest cache line size in the platform. This is known only 142 * to the platform as it might have a combination of integrated and external 143 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 144 * line at any cache level. They could belong to different cpus/clusters & 145 * get written while being protected by different locks causing corruption of 146 * a valid mailbox address. 147 */ 148 #define CACHE_WRITEBACK_SHIFT 6 149 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 150 151 #endif /* __PLATFORM_DEF_H__ */ 152