12f2abcf4SHaojian Zhuang/* 22f2abcf4SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 32f2abcf4SHaojian Zhuang * 42f2abcf4SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 52f2abcf4SHaojian Zhuang */ 62f2abcf4SHaojian Zhuang 7c3cf06f1SAntonio Nino Diaz#ifndef PLAT_MACROS_S 8c3cf06f1SAntonio Nino Diaz#define PLAT_MACROS_S 92f2abcf4SHaojian Zhuang 10*09d40e0eSAntonio Nino Diaz#include <drivers/arm/cci.h> 11*09d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv2.h> 12ee1ebbd1SIsla Mitchell#include <hi3660.h> 132f2abcf4SHaojian Zhuang#include <platform_def.h> 142f2abcf4SHaojian Zhuang 152f2abcf4SHaojian Zhuang.section .rodata.gic_reg_name, "aS" 162f2abcf4SHaojian Zhuanggicc_regs: 172f2abcf4SHaojian Zhuang .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 182f2abcf4SHaojian Zhuanggicd_pend_reg: 19492a504cSHaojian Zhuang .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 202f2abcf4SHaojian Zhuangnewline: 212f2abcf4SHaojian Zhuang .asciz "\n" 222f2abcf4SHaojian Zhuangspacer: 232f2abcf4SHaojian Zhuang .asciz ":\t\t0x" 242f2abcf4SHaojian Zhuang 252f2abcf4SHaojian Zhuang.section .rodata.cci_reg_name, "aS" 262f2abcf4SHaojian Zhuangcci_iface_regs: 272f2abcf4SHaojian Zhuang .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 282f2abcf4SHaojian Zhuang 292f2abcf4SHaojian Zhuang/* --------------------------------------------- 302f2abcf4SHaojian Zhuang * The below macro prints out relevant GIC 312f2abcf4SHaojian Zhuang * registers whenever an unhandled exception is 322f2abcf4SHaojian Zhuang * taken in BL31. 332f2abcf4SHaojian Zhuang * --------------------------------------------- 342f2abcf4SHaojian Zhuang */ 352f2abcf4SHaojian Zhuang.macro plat_crash_print_regs 362f2abcf4SHaojian Zhuang mov_imm x16, GICD_REG_BASE 372f2abcf4SHaojian Zhuang mov_imm x17, GICC_REG_BASE 382f2abcf4SHaojian Zhuang 392f2abcf4SHaojian Zhuang /* Load the gicc reg list to x6 */ 402f2abcf4SHaojian Zhuang adr x6, gicc_regs 412f2abcf4SHaojian Zhuang /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 422f2abcf4SHaojian Zhuang ldr w8, [x17, #GICC_HPPIR] 432f2abcf4SHaojian Zhuang ldr w9, [x17, #GICC_AHPPIR] 442f2abcf4SHaojian Zhuang ldr w10, [x17, #GICC_CTLR] 452f2abcf4SHaojian Zhuang /* Store to the crash buf and print to cosole */ 462f2abcf4SHaojian Zhuang bl str_in_crash_buf_print 472f2abcf4SHaojian Zhuang 482f2abcf4SHaojian Zhuang /* Print the GICD_ISPENDR regs */ 492f2abcf4SHaojian Zhuang add x7, x16, #GICD_ISPENDR 502f2abcf4SHaojian Zhuang adr x4, gicd_pend_reg 512f2abcf4SHaojian Zhuang bl asm_print_str 522f2abcf4SHaojian Zhuang2: 532f2abcf4SHaojian Zhuang sub x4, x7, x16 542f2abcf4SHaojian Zhuang cmp x4, #0x280 552f2abcf4SHaojian Zhuang b.eq 1f 562f2abcf4SHaojian Zhuang bl asm_print_hex 572f2abcf4SHaojian Zhuang adr x4, spacer 582f2abcf4SHaojian Zhuang bl asm_print_str 592f2abcf4SHaojian Zhuang ldr x4, [x7], #8 602f2abcf4SHaojian Zhuang bl asm_print_hex 612f2abcf4SHaojian Zhuang adr x4, newline 622f2abcf4SHaojian Zhuang bl asm_print_str 632f2abcf4SHaojian Zhuang b 2b 642f2abcf4SHaojian Zhuang1: 652f2abcf4SHaojian Zhuang adr x6, cci_iface_regs 662f2abcf4SHaojian Zhuang /* Store in x7 the base address of the first interface */ 672f2abcf4SHaojian Zhuang mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \ 682f2abcf4SHaojian Zhuang CCI400_SL_IFACE3_CLUSTER_IX)) 692f2abcf4SHaojian Zhuang ldr w8, [x7, #SNOOP_CTRL_REG] 702f2abcf4SHaojian Zhuang /* Store in x7 the base address of the second interface */ 712f2abcf4SHaojian Zhuang mov_imm x7, (CCI400_REG_BASE + SLAVE_IFACE_OFFSET( \ 722f2abcf4SHaojian Zhuang CCI400_SL_IFACE4_CLUSTER_IX)) 732f2abcf4SHaojian Zhuang ldr w9, [x7, #SNOOP_CTRL_REG] 742f2abcf4SHaojian Zhuang /* Store to the crash buf and print to console */ 752f2abcf4SHaojian Zhuang bl str_in_crash_buf_print 762f2abcf4SHaojian Zhuang.endm 772f2abcf4SHaojian Zhuang 78c3cf06f1SAntonio Nino Diaz#endif /* PLAT_MACROS_S */ 79