1*e618c621SLukas Hanel/* 2*e618c621SLukas Hanel * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3*e618c621SLukas Hanel * 4*e618c621SLukas Hanel * SPDX-License-Identifier: BSD-3-Clause 5*e618c621SLukas Hanel */ 6*e618c621SLukas Hanel#ifndef PLAT_LD_S 7*e618c621SLukas Hanel#define PLAT_LD_S 8*e618c621SLukas Hanel 9*e618c621SLukas Hanel#include <lib/xlat_tables/xlat_tables_defs.h> 10*e618c621SLukas Hanel 11*e618c621SLukas HanelMEMORY { 12*e618c621SLukas Hanel RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE 13*e618c621SLukas Hanel} 14*e618c621SLukas Hanel 15*e618c621SLukas HanelSECTIONS 16*e618c621SLukas Hanel{ 17*e618c621SLukas Hanel ram2_region (NOLOAD) : { 18*e618c621SLukas Hanel *(ram2_region) 19*e618c621SLukas Hanel }>RAM2 20*e618c621SLukas Hanel} 21*e618c621SLukas Hanel 22*e618c621SLukas Hanel#endif /* PLAT_LD_S */ 23