1e618c621SLukas Hanel/* 2*da04341eSChris Kay * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. 3e618c621SLukas Hanel * 4e618c621SLukas Hanel * SPDX-License-Identifier: BSD-3-Clause 5e618c621SLukas Hanel */ 6e618c621SLukas Hanel#ifndef PLAT_LD_S 7e618c621SLukas Hanel#define PLAT_LD_S 8e618c621SLukas Hanel 9e618c621SLukas Hanel#include <lib/xlat_tables/xlat_tables_defs.h> 10e618c621SLukas Hanel 11e618c621SLukas HanelMEMORY { 12e618c621SLukas Hanel RAM2 (rw): ORIGIN = DDR2_SEC_BASE, LENGTH = DDR2_SEC_SIZE 13e618c621SLukas Hanel} 14e618c621SLukas Hanel 15e618c621SLukas HanelSECTIONS 16e618c621SLukas Hanel{ 17*da04341eSChris Kay .ram2_region (NOLOAD) : { 18*da04341eSChris Kay *(.ram2_region) 19e618c621SLukas Hanel }>RAM2 20e618c621SLukas Hanel} 21e618c621SLukas Hanel 22e618c621SLukas Hanel#endif /* PLAT_LD_S */ 23