1 /* 2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef HIKEY960_DEF_H 8 #define HIKEY960_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <plat/common/common_def.h> 12 13 #define DDR_BASE 0x0 14 #define DDR_SIZE 0xE0000000 15 16 #define DEVICE_BASE 0xE0000000 17 #define DEVICE_SIZE 0x20000000 18 19 /* Memory location options for TSP */ 20 #define HIKEY960_SRAM_ID 0 21 #define HIKEY960_DRAM_ID 1 22 23 /* 24 * DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several 25 * regions: 26 * - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE 27 * - Secure DDR (default is the top 64MB) used by OP-TEE 28 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 29 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 30 * - Non-secure DDR (8MB) reserved for OP-TEE's future use 31 */ 32 #define DDR_SEC_SIZE 0x04000000 /* reserve 64MB secure memory */ 33 #define DDR_SEC_BASE 0x3F000000 34 #define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */ 35 #define DDR_SEC_CONFIG_BASE 0x43000000 36 37 #define DDR_SDP_SIZE 0x00400000 38 #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ 39 DDR_SDP_SIZE) 40 41 /* 42 * PL011 related constants 43 */ 44 #define PL011_UART5_BASE 0xFDF05000 45 #define PL011_UART6_BASE 0xFFF32000 46 #define PL011_BAUDRATE 115200 47 #define PL011_UART_CLK_IN_HZ 19200000 48 49 #define UFS_BASE 0 50 51 #define HIKEY960_UFS_DESC_BASE 0x20000000 52 #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ 53 #define HIKEY960_UFS_DATA_BASE 0x10000000 54 #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ 55 56 #endif /* HIKEY960_DEF_H */ 57