12f2abcf4SHaojian Zhuang /* 2e0eea337SArthur Cassegrain * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 32f2abcf4SHaojian Zhuang * 42f2abcf4SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 52f2abcf4SHaojian Zhuang */ 62f2abcf4SHaojian Zhuang 7c3cf06f1SAntonio Nino Diaz #ifndef HIKEY960_DEF_H 8c3cf06f1SAntonio Nino Diaz #define HIKEY960_DEF_H 92f2abcf4SHaojian Zhuang 1009d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h> 1109d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 122f2abcf4SHaojian Zhuang 132f2abcf4SHaojian Zhuang #define DDR_BASE 0x0 1412e0ca46SJoel Hutton #define DDR_SIZE 0xE0000000 152f2abcf4SHaojian Zhuang 162f2abcf4SHaojian Zhuang #define DEVICE_BASE 0xE0000000 172f2abcf4SHaojian Zhuang #define DEVICE_SIZE 0x20000000 182f2abcf4SHaojian Zhuang 195e3325e7SVictor Chong /* Memory location options for TSP */ 205e3325e7SVictor Chong #define HIKEY960_SRAM_ID 0 215e3325e7SVictor Chong #define HIKEY960_DRAM_ID 1 225e3325e7SVictor Chong 235e3325e7SVictor Chong /* 246971642dSLukas Hanel * DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several 255e3325e7SVictor Chong * regions: 266971642dSLukas Hanel * - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE 27*e618c621SLukas Hanel * - Datastore for SPMC_AT_EL3 (4MB at the top) used by BL31 28*e618c621SLukas Hanel * - Secure DDR (default is the top 60MB) used by OP-TEE 295e3325e7SVictor Chong * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 305e3325e7SVictor Chong * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 315e3325e7SVictor Chong * - Non-secure DDR (8MB) reserved for OP-TEE's future use 325e3325e7SVictor Chong */ 33*e618c621SLukas Hanel #define DDR_SEC_SIZE 0x03C00000 /* reserve 60MB secure memory */ 345e3325e7SVictor Chong #define DDR_SEC_BASE 0x3F000000 35*e618c621SLukas Hanel #define DDR2_SEC_SIZE 0x00400000 /* SPMC_AT_EL3: 4MB for BL31 RAM2 */ 36*e618c621SLukas Hanel #define DDR2_SEC_BASE 0x42C00000 376971642dSLukas Hanel #define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */ 386971642dSLukas Hanel #define DDR_SEC_CONFIG_BASE 0x43000000 395e3325e7SVictor Chong 405e3325e7SVictor Chong #define DDR_SDP_SIZE 0x00400000 415e3325e7SVictor Chong #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ 425e3325e7SVictor Chong DDR_SDP_SIZE) 435e3325e7SVictor Chong 442f2abcf4SHaojian Zhuang /* 452f2abcf4SHaojian Zhuang * PL011 related constants 462f2abcf4SHaojian Zhuang */ 472f2abcf4SHaojian Zhuang #define PL011_UART5_BASE 0xFDF05000 482f2abcf4SHaojian Zhuang #define PL011_UART6_BASE 0xFFF32000 492f2abcf4SHaojian Zhuang #define PL011_BAUDRATE 115200 502f2abcf4SHaojian Zhuang #define PL011_UART_CLK_IN_HZ 19200000 512f2abcf4SHaojian Zhuang 522f2abcf4SHaojian Zhuang #define UFS_BASE 0 532f2abcf4SHaojian Zhuang 542f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DESC_BASE 0x20000000 552f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ 562f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DATA_BASE 0x10000000 572f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ 582f2abcf4SHaojian Zhuang 59c3cf06f1SAntonio Nino Diaz #endif /* HIKEY960_DEF_H */ 60