1*2f2abcf4SHaojian Zhuang /* 2*2f2abcf4SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*2f2abcf4SHaojian Zhuang * 4*2f2abcf4SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5*2f2abcf4SHaojian Zhuang */ 6*2f2abcf4SHaojian Zhuang 7*2f2abcf4SHaojian Zhuang #ifndef __HIKEY960_DEF_H__ 8*2f2abcf4SHaojian Zhuang #define __HIKEY960_DEF_H__ 9*2f2abcf4SHaojian Zhuang 10*2f2abcf4SHaojian Zhuang #include <common_def.h> 11*2f2abcf4SHaojian Zhuang #include <tbbr_img_def.h> 12*2f2abcf4SHaojian Zhuang 13*2f2abcf4SHaojian Zhuang #define DDR_BASE 0x0 14*2f2abcf4SHaojian Zhuang #define DDR_SIZE 0xC0000000 15*2f2abcf4SHaojian Zhuang 16*2f2abcf4SHaojian Zhuang #define DEVICE_BASE 0xE0000000 17*2f2abcf4SHaojian Zhuang #define DEVICE_SIZE 0x20000000 18*2f2abcf4SHaojian Zhuang 19*2f2abcf4SHaojian Zhuang /* 20*2f2abcf4SHaojian Zhuang * PL011 related constants 21*2f2abcf4SHaojian Zhuang */ 22*2f2abcf4SHaojian Zhuang #define PL011_UART5_BASE 0xFDF05000 23*2f2abcf4SHaojian Zhuang #define PL011_UART6_BASE 0xFFF32000 24*2f2abcf4SHaojian Zhuang #define PL011_BAUDRATE 115200 25*2f2abcf4SHaojian Zhuang #define PL011_UART_CLK_IN_HZ 19200000 26*2f2abcf4SHaojian Zhuang 27*2f2abcf4SHaojian Zhuang #define UFS_BASE 0 28*2f2abcf4SHaojian Zhuang /* FIP partition */ 29*2f2abcf4SHaojian Zhuang #define HIKEY960_FIP_BASE (UFS_BASE + 0x1400000) 30*2f2abcf4SHaojian Zhuang #define HIKEY960_FIP_MAX_SIZE (12 << 20) 31*2f2abcf4SHaojian Zhuang 32*2f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DESC_BASE 0x20000000 33*2f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ 34*2f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DATA_BASE 0x10000000 35*2f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ 36*2f2abcf4SHaojian Zhuang 37*2f2abcf4SHaojian Zhuang #endif /* __HIKEY960_DEF_H__ */ 38