12f2abcf4SHaojian Zhuang /* 22f2abcf4SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 32f2abcf4SHaojian Zhuang * 42f2abcf4SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 52f2abcf4SHaojian Zhuang */ 62f2abcf4SHaojian Zhuang 7c3cf06f1SAntonio Nino Diaz #ifndef HIKEY960_DEF_H 8c3cf06f1SAntonio Nino Diaz #define HIKEY960_DEF_H 92f2abcf4SHaojian Zhuang 1009d40e0eSAntonio Nino Diaz #include <common/tbbr/tbbr_img_def.h> 1109d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 122f2abcf4SHaojian Zhuang 132f2abcf4SHaojian Zhuang #define DDR_BASE 0x0 14*12e0ca46SJoel Hutton #define DDR_SIZE 0xE0000000 152f2abcf4SHaojian Zhuang 162f2abcf4SHaojian Zhuang #define DEVICE_BASE 0xE0000000 172f2abcf4SHaojian Zhuang #define DEVICE_SIZE 0x20000000 182f2abcf4SHaojian Zhuang 195e3325e7SVictor Chong /* Memory location options for TSP */ 205e3325e7SVictor Chong #define HIKEY960_SRAM_ID 0 215e3325e7SVictor Chong #define HIKEY960_DRAM_ID 1 225e3325e7SVictor Chong 235e3325e7SVictor Chong /* 245e3325e7SVictor Chong * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several 255e3325e7SVictor Chong * regions: 265e3325e7SVictor Chong * - Secure DDR (default is the top 16MB) used by OP-TEE 275e3325e7SVictor Chong * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 285e3325e7SVictor Chong * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 295e3325e7SVictor Chong * - Non-secure DDR (8MB) reserved for OP-TEE's future use 305e3325e7SVictor Chong */ 315e3325e7SVictor Chong #define DDR_SEC_SIZE 0x01000000 325e3325e7SVictor Chong #define DDR_SEC_BASE 0x3F000000 335e3325e7SVictor Chong 345e3325e7SVictor Chong #define DDR_SDP_SIZE 0x00400000 355e3325e7SVictor Chong #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ 365e3325e7SVictor Chong DDR_SDP_SIZE) 375e3325e7SVictor Chong 382f2abcf4SHaojian Zhuang /* 392f2abcf4SHaojian Zhuang * PL011 related constants 402f2abcf4SHaojian Zhuang */ 412f2abcf4SHaojian Zhuang #define PL011_UART5_BASE 0xFDF05000 422f2abcf4SHaojian Zhuang #define PL011_UART6_BASE 0xFFF32000 432f2abcf4SHaojian Zhuang #define PL011_BAUDRATE 115200 442f2abcf4SHaojian Zhuang #define PL011_UART_CLK_IN_HZ 19200000 452f2abcf4SHaojian Zhuang 462f2abcf4SHaojian Zhuang #define UFS_BASE 0 472f2abcf4SHaojian Zhuang /* FIP partition */ 482f2abcf4SHaojian Zhuang #define HIKEY960_FIP_BASE (UFS_BASE + 0x1400000) 492f2abcf4SHaojian Zhuang #define HIKEY960_FIP_MAX_SIZE (12 << 20) 502f2abcf4SHaojian Zhuang 512f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DESC_BASE 0x20000000 522f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ 532f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DATA_BASE 0x10000000 542f2abcf4SHaojian Zhuang #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ 552f2abcf4SHaojian Zhuang 56c3cf06f1SAntonio Nino Diaz #endif /* HIKEY960_DEF_H */ 57