1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <debug.h> 8 #include <delay_timer.h> 9 #include <hi3660.h> 10 #include <mmio.h> 11 12 #include "hikey960_private.h" 13 14 void hikey960_clk_init(void) 15 { 16 /* change ldi0 sel to ppll2 */ 17 mmio_write_32(0xfff350b4, 0xf0002000); 18 /* ldi0 20' */ 19 mmio_write_32(0xfff350bc, 0xfc004c00); 20 } 21 22 void hikey960_pmu_init(void) 23 { 24 /* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */ 25 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); 26 } 27 28 static void hikey960_enable_ppll3(void) 29 { 30 /* enable ppll3 */ 31 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); 32 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); 33 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); 34 } 35 36 static void bus_idle_clear(unsigned int value) 37 { 38 unsigned int pmc_value, value1, value2; 39 int timeout = 100; 40 41 pmc_value = value << 16; 42 pmc_value &= ~value; 43 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); 44 45 for (;;) { 46 value1 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLEACK_REG); 47 value2 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLE_REG); 48 if (((value1 & value) == 0) && ((value2 & value) == 0)) 49 break; 50 udelay(1); 51 timeout--; 52 if (timeout <= 0) { 53 WARN("%s timeout\n", __func__); 54 break; 55 } 56 } 57 } 58 59 static void set_vivobus_power_up(void) 60 { 61 /* clk enable */ 62 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); 63 mmio_write_32(CRG_PEREN0_REG, 0x00001000); 64 } 65 66 static void set_dss_power_up(void) 67 { 68 /* set edc0 133MHz = 1600MHz / 12 */ 69 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); 70 /* set ldi0 ppl0 */ 71 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); 72 /* set ldi0 133MHz, 1600MHz / 12 */ 73 mmio_write_32(CRG_CLKDIV5_REG, 0xfc002c00); 74 /* mtcmos on */ 75 mmio_write_32(CRG_PERPWREN_REG, 0x00000020); 76 udelay(100); 77 /* DISP CRG */ 78 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000010); 79 /* clk enable */ 80 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 81 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 82 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 83 udelay(1); 84 /* clk disable */ 85 mmio_write_32(CRG_PERDIS3_REG, 0x0003b000); 86 mmio_write_32(CRG_PERDIS0_REG, 0x00002000); 87 mmio_write_32(CRG_CLKDIV18_REG, 0x01400000); 88 udelay(1); 89 /* iso disable */ 90 mmio_write_32(CRG_ISODIS_REG, 0x00000040); 91 /* unreset */ 92 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000006); 93 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000c00); 94 /* clk enable */ 95 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 96 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 97 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 98 /* bus idle clear */ 99 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_DSS); 100 /* set edc0 400MHz for 2K 1600MHz / 4 */ 101 mmio_write_32(CRG_CLKDIV5_REG, 0x003f0003); 102 /* set ldi 266MHz, 1600MHz / 6 */ 103 mmio_write_32(CRG_CLKDIV5_REG, 0xfc001400); 104 } 105 106 static void set_vcodec_power_up(void) 107 { 108 /* clk enable */ 109 mmio_write_32(CRG_CLKDIV20_REG, 0x00040004); 110 mmio_write_32(CRG_PEREN0_REG, 0x00000060); 111 mmio_write_32(CRG_PEREN2_REG, 0x10000000); 112 /* unreset */ 113 mmio_write_32(CRG_PERRSTDIS0_REG, 0x00000018); 114 /* bus idle clear */ 115 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VCODEC); 116 } 117 118 static void set_vdec_power_up(void) 119 { 120 /* mtcmos on */ 121 mmio_write_32(CRG_PERPWREN_REG, 0x00000004); 122 udelay(100); 123 /* clk enable */ 124 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 125 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 126 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 127 udelay(1); 128 /* clk disable */ 129 mmio_write_32(CRG_PERDIS3_REG, 0x00000800); 130 mmio_write_32(CRG_PERDIS2_REG, 0x20080000); 131 mmio_write_32(CRG_CLKDIV18_REG, 0x80000000); 132 udelay(1); 133 /* iso disable */ 134 mmio_write_32(CRG_ISODIS_REG, 0x00000004); 135 /* unreset */ 136 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000200); 137 /* clk enable */ 138 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 139 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 140 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 141 /* bus idle clear */ 142 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VDEC); 143 } 144 145 static void set_venc_power_up(void) 146 { 147 /* set venc ppll3 */ 148 mmio_write_32(CRG_CLKDIV8_REG, 0x18001000); 149 /* set venc 258MHz, 1290MHz / 5 */ 150 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00100); 151 /* mtcmos on */ 152 mmio_write_32(CRG_PERPWREN_REG, 0x00000002); 153 udelay(100); 154 /* clk enable */ 155 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 156 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 157 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 158 udelay(1); 159 /* clk disable */ 160 mmio_write_32(CRG_PERDIS3_REG, 0x00000400); 161 mmio_write_32(CRG_PERDIS2_REG, 0x40000100); 162 mmio_write_32(CRG_CLKDIV19_REG, 0x00010000); 163 udelay(1); 164 /* iso disable */ 165 mmio_write_32(CRG_ISODIS_REG, 0x00000002); 166 /* unreset */ 167 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000100); 168 /* clk enable */ 169 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 170 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 171 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 172 /* bus idle clear */ 173 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VENC); 174 /* set venc 645MHz, 1290MHz / 2 */ 175 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00040); 176 } 177 178 static void set_isp_power_up(void) 179 { 180 /* mtcmos on */ 181 mmio_write_32(CRG_PERPWREN_REG, 0x00000001); 182 udelay(100); 183 /* clk enable */ 184 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 185 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 186 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 187 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 188 udelay(1); 189 /* clk disable */ 190 mmio_write_32(CRG_PERDIS5_REG, 0x01000010); 191 mmio_write_32(CRG_PERDIS3_REG, 0x0bf00000); 192 mmio_write_32(CRG_CLKDIV18_REG, 0x70000000); 193 mmio_write_32(CRG_CLKDIV20_REG, 0x00100000); 194 udelay(1); 195 /* iso disable */ 196 mmio_write_32(CRG_ISODIS_REG, 0x00000001); 197 /* unreset */ 198 mmio_write_32(CRG_ISP_SEC_RSTDIS_REG, 0x0000002f); 199 /* clk enable */ 200 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 201 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 202 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 203 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 204 /* bus idle clear */ 205 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_ISP); 206 /* csi clk enable */ 207 mmio_write_32(CRG_PEREN3_REG, 0x00700000); 208 } 209 210 static void set_ivp_power_up(void) 211 { 212 /* set ivp ppll0 */ 213 mmio_write_32(CRG_CLKDIV0_REG, 0xc0000000); 214 /* set ivp 267MHz, 1600MHz / 6 */ 215 mmio_write_32(CRG_CLKDIV0_REG, 0x3c001400); 216 /* mtcmos on */ 217 mmio_write_32(CRG_PERPWREN_REG, 0x00200000); 218 udelay(100); 219 /* IVP CRG unreset */ 220 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000001); 221 /* clk enable */ 222 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 223 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 224 udelay(1); 225 /* clk disable */ 226 mmio_write_32(CRG_PERDIS4_REG, 0x000000a8); 227 mmio_write_32(CRG_CLKDIV20_REG, 0x02000000); 228 udelay(1); 229 /* iso disable */ 230 mmio_write_32(CRG_ISODIS_REG, 0x01000000); 231 /* unreset */ 232 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000002); 233 /* clk enable */ 234 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 235 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 236 /* bus idle clear */ 237 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_IVP); 238 /* set ivp 533MHz, 1600MHz / 3 */ 239 mmio_write_32(CRG_CLKDIV0_REG, 0x3c000800); 240 } 241 242 static void set_audio_power_up(void) 243 { 244 unsigned int ret; 245 int timeout = 100; 246 /* mtcmos on */ 247 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000001); 248 udelay(100); 249 /* clk enable */ 250 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 251 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 252 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 253 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 254 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 255 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 256 udelay(1); 257 /* clk disable */ 258 mmio_write_32(SCTRL_SCPERDIS1_REG, 0x0000000f); 259 mmio_write_32(SCTRL_SCPERDIS0_REG, 0x0c000000); 260 mmio_write_32(CRG_PERDIS5_REG, 0x00000080); 261 mmio_write_32(CRG_PERDIS0_REG, 0x04000000); 262 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010000); 263 mmio_write_32(CRG_CLKDIV19_REG, 0x80100000); 264 udelay(1); 265 /* iso disable */ 266 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000001); 267 udelay(1); 268 /* unreset */ 269 mmio_write_32(SCTRL_PERRSTDIS1_SEC_REG, 0x00000001); 270 mmio_write_32(SCTRL_SCPERRSTDIS0_REG, 0x00000780); 271 /* clk enable */ 272 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 273 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 274 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 275 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 276 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 277 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 278 /* bus idle clear */ 279 mmio_write_32(SCTRL_SCPERCTRL7_REG, 0x00040000); 280 for (;;) { 281 ret = mmio_read_32(SCTRL_SCPERSTAT6_REG); 282 if (((ret & (1 << 5)) == 0) && ((ret & (1 << 8)) == 0)) 283 break; 284 udelay(1); 285 timeout--; 286 if (timeout <= 0) { 287 WARN("%s timeout\n", __func__); 288 break; 289 } 290 } 291 mmio_write_32(ASP_CFG_MMBUF_CTRL_REG, 0x00ff0000); 292 } 293 294 static void set_pcie_power_up(void) 295 { 296 /* mtcmos on */ 297 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000010); 298 udelay(100); 299 /* clk enable */ 300 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 301 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 302 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 303 udelay(1); 304 /* clk disable */ 305 mmio_write_32(SCTRL_SCPERDIS2_REG, 0x00104000); 306 mmio_write_32(CRG_PERDIS7_REG, 0x000003a0); 307 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000000); 308 udelay(1); 309 /* iso disable */ 310 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000030); 311 /* unreset */ 312 mmio_write_32(CRG_PERRSTDIS3_REG, 0x8c000000); 313 /* clk enable */ 314 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 315 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 316 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 317 } 318 319 static void ispfunc_enable(void) 320 { 321 /* enable ispfunc. Otherwise powerup isp_srt causes exception. */ 322 mmio_write_32(0xfff35000, 0x00000008); 323 mmio_write_32(0xfff35460, 0xc004ffff); 324 mmio_write_32(0xfff35030, 0x02000000); 325 mdelay(10); 326 } 327 328 static void isps_control_clock(int flag) 329 { 330 unsigned int ret; 331 332 /* flag: 0 -- disable clock, 1 -- enable clock */ 333 if (flag) { 334 ret = mmio_read_32(0xe8420364); 335 ret |= 1; 336 mmio_write_32(0xe8420364, ret); 337 } else { 338 ret = mmio_read_32(0xe8420364); 339 ret &= ~1; 340 mmio_write_32(0xe8420364, ret); 341 } 342 } 343 344 static void set_isp_srt_power_up(void) 345 { 346 unsigned int ret; 347 348 ispfunc_enable(); 349 /* reset */ 350 mmio_write_32(0xe8420374, 0x00000001); 351 mmio_write_32(0xe8420350, 0x00000000); 352 mmio_write_32(0xe8420358, 0x00000000); 353 /* mtcmos on */ 354 mmio_write_32(0xfff35150, 0x00400000); 355 udelay(100); 356 /* clk enable */ 357 isps_control_clock(1); 358 udelay(1); 359 isps_control_clock(0); 360 udelay(1); 361 /* iso disable */ 362 mmio_write_32(0xfff35148, 0x08000000); 363 /* unreset */ 364 ret = mmio_read_32(0xe8420374); 365 ret &= ~0x1; 366 mmio_write_32(0xe8420374, ret); 367 /* clk enable */ 368 isps_control_clock(1); 369 /* enable clock gating for accessing csi registers */ 370 mmio_write_32(0xe8420010, ~0); 371 } 372 373 void hikey960_regulator_enable(void) 374 { 375 set_vivobus_power_up(); 376 hikey960_enable_ppll3(); 377 set_dss_power_up(); 378 set_vcodec_power_up(); 379 set_vdec_power_up(); 380 set_venc_power_up(); 381 set_isp_power_up(); 382 set_ivp_power_up(); 383 set_audio_power_up(); 384 set_pcie_power_up(); 385 set_isp_srt_power_up(); 386 387 /* set ISP_CORE_CTRL_S to unsecure mode */ 388 mmio_write_32(0xe8583800, 0x7); 389 /* set ISP_SUB_CTRL_S to unsecure mode */ 390 mmio_write_32(0xe8583804, 0xf); 391 } 392 393 void hikey960_tzc_init(void) 394 { 395 mmio_write_32(TZC_EN0_REG, 0x7fbff066); 396 mmio_write_32(TZC_EN1_REG, 0xfffff5fc); 397 mmio_write_32(TZC_EN2_REG, 0x0007005c); 398 mmio_write_32(TZC_EN3_REG, 0x37030700); 399 mmio_write_32(TZC_EN4_REG, 0xf63fefae); 400 mmio_write_32(TZC_EN5_REG, 0x000410fd); 401 mmio_write_32(TZC_EN6_REG, 0x0063ff68); 402 mmio_write_32(TZC_EN7_REG, 0x030000f3); 403 mmio_write_32(TZC_EN8_REG, 0x00000007); 404 } 405 406 void hikey960_peri_init(void) 407 { 408 /* unreset */ 409 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1); 410 } 411 412 void hikey960_pinmux_init(void) 413 { 414 unsigned int id; 415 416 hikey960_read_boardid(&id); 417 if (id == 5301) { 418 /* hikey960 hardware v2 */ 419 /* GPIO150: LED */ 420 mmio_write_32(IOMG_FIX_006_REG, 0); 421 /* GPIO151: LED */ 422 mmio_write_32(IOMG_FIX_007_REG, 0); 423 /* GPIO189: LED */ 424 mmio_write_32(IOMG_AO_011_REG, 0); 425 /* GPIO190: LED */ 426 mmio_write_32(IOMG_AO_012_REG, 0); 427 /* GPIO46 */ 428 mmio_write_32(IOMG_044_REG, 0); 429 /* GPIO202 */ 430 mmio_write_32(IOMG_AO_023_REG, 0); 431 /* GPIO206 */ 432 mmio_write_32(IOMG_AO_026_REG, 0); 433 /* GPIO219 - PD pullup */ 434 mmio_write_32(IOMG_AO_039_REG, 0); 435 mmio_write_32(IOCG_AO_043_REG, 1 << 0); 436 } 437 /* GPIO005 - PMU SSI, 10mA */ 438 mmio_write_32(IOCG_006_REG, 2 << 4); 439 /* GPIO213 - PCIE_CLKREQ_N */ 440 mmio_write_32(IOMG_AO_033_REG, 1); 441 } 442