1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/arm/pl061_gpio.h> 9 #include <drivers/delay_timer.h> 10 #include <lib/mmio.h> 11 12 #include <hi3660.h> 13 #include "hikey960_private.h" 14 15 void hikey960_clk_init(void) 16 { 17 /* change ldi0 sel to ppll2 */ 18 mmio_write_32(0xfff350b4, 0xf0002000); 19 /* ldi0 20' */ 20 mmio_write_32(0xfff350bc, 0xfc004c00); 21 } 22 23 void hikey960_pmu_init(void) 24 { 25 /* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */ 26 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); 27 } 28 29 static void hikey960_enable_ppll3(void) 30 { 31 /* enable ppll3 */ 32 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); 33 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); 34 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); 35 } 36 37 static void bus_idle_clear(unsigned int value) 38 { 39 unsigned int pmc_value, value1, value2; 40 int timeout = 100; 41 42 pmc_value = value << 16; 43 pmc_value &= ~value; 44 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); 45 46 for (;;) { 47 value1 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLEACK_REG); 48 value2 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLE_REG); 49 if (((value1 & value) == 0) && ((value2 & value) == 0)) 50 break; 51 udelay(1); 52 timeout--; 53 if (timeout <= 0) { 54 WARN("%s timeout\n", __func__); 55 break; 56 } 57 } 58 } 59 60 static void set_vivobus_power_up(void) 61 { 62 /* clk enable */ 63 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); 64 mmio_write_32(CRG_PEREN0_REG, 0x00001000); 65 } 66 67 static void set_dss_power_up(void) 68 { 69 /* set edc0 133MHz = 1600MHz / 12 */ 70 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); 71 /* set ldi0 ppl0 */ 72 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); 73 /* set ldi0 133MHz, 1600MHz / 12 */ 74 mmio_write_32(CRG_CLKDIV5_REG, 0xfc002c00); 75 /* mtcmos on */ 76 mmio_write_32(CRG_PERPWREN_REG, 0x00000020); 77 udelay(100); 78 /* DISP CRG */ 79 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000010); 80 /* clk enable */ 81 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 82 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 83 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 84 udelay(1); 85 /* clk disable */ 86 mmio_write_32(CRG_PERDIS3_REG, 0x0003b000); 87 mmio_write_32(CRG_PERDIS0_REG, 0x00002000); 88 mmio_write_32(CRG_CLKDIV18_REG, 0x01400000); 89 udelay(1); 90 /* iso disable */ 91 mmio_write_32(CRG_ISODIS_REG, 0x00000040); 92 /* unreset */ 93 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000006); 94 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000c00); 95 /* clk enable */ 96 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 97 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 98 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 99 /* bus idle clear */ 100 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_DSS); 101 /* set edc0 400MHz for 2K 1600MHz / 4 */ 102 mmio_write_32(CRG_CLKDIV5_REG, 0x003f0003); 103 /* set ldi 266MHz, 1600MHz / 6 */ 104 mmio_write_32(CRG_CLKDIV5_REG, 0xfc001400); 105 } 106 107 static void set_vcodec_power_up(void) 108 { 109 /* clk enable */ 110 mmio_write_32(CRG_CLKDIV20_REG, 0x00040004); 111 mmio_write_32(CRG_PEREN0_REG, 0x00000060); 112 mmio_write_32(CRG_PEREN2_REG, 0x10000000); 113 /* unreset */ 114 mmio_write_32(CRG_PERRSTDIS0_REG, 0x00000018); 115 /* bus idle clear */ 116 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VCODEC); 117 } 118 119 static void set_vdec_power_up(void) 120 { 121 /* mtcmos on */ 122 mmio_write_32(CRG_PERPWREN_REG, 0x00000004); 123 udelay(100); 124 /* clk enable */ 125 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 126 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 127 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 128 udelay(1); 129 /* clk disable */ 130 mmio_write_32(CRG_PERDIS3_REG, 0x00000800); 131 mmio_write_32(CRG_PERDIS2_REG, 0x20080000); 132 mmio_write_32(CRG_CLKDIV18_REG, 0x80000000); 133 udelay(1); 134 /* iso disable */ 135 mmio_write_32(CRG_ISODIS_REG, 0x00000004); 136 /* unreset */ 137 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000200); 138 /* clk enable */ 139 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 140 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 141 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 142 /* bus idle clear */ 143 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VDEC); 144 } 145 146 static void set_venc_power_up(void) 147 { 148 /* set venc ppll3 */ 149 mmio_write_32(CRG_CLKDIV8_REG, 0x18001000); 150 /* set venc 258MHz, 1290MHz / 5 */ 151 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00100); 152 /* mtcmos on */ 153 mmio_write_32(CRG_PERPWREN_REG, 0x00000002); 154 udelay(100); 155 /* clk enable */ 156 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 157 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 158 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 159 udelay(1); 160 /* clk disable */ 161 mmio_write_32(CRG_PERDIS3_REG, 0x00000400); 162 mmio_write_32(CRG_PERDIS2_REG, 0x40000100); 163 mmio_write_32(CRG_CLKDIV19_REG, 0x00010000); 164 udelay(1); 165 /* iso disable */ 166 mmio_write_32(CRG_ISODIS_REG, 0x00000002); 167 /* unreset */ 168 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000100); 169 /* clk enable */ 170 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 171 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 172 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 173 /* bus idle clear */ 174 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VENC); 175 /* set venc 645MHz, 1290MHz / 2 */ 176 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00040); 177 } 178 179 static void set_isp_power_up(void) 180 { 181 /* mtcmos on */ 182 mmio_write_32(CRG_PERPWREN_REG, 0x00000001); 183 udelay(100); 184 /* clk enable */ 185 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 186 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 187 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 188 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 189 udelay(1); 190 /* clk disable */ 191 mmio_write_32(CRG_PERDIS5_REG, 0x01000010); 192 mmio_write_32(CRG_PERDIS3_REG, 0x0bf00000); 193 mmio_write_32(CRG_CLKDIV18_REG, 0x70000000); 194 mmio_write_32(CRG_CLKDIV20_REG, 0x00100000); 195 udelay(1); 196 /* iso disable */ 197 mmio_write_32(CRG_ISODIS_REG, 0x00000001); 198 /* unreset */ 199 mmio_write_32(CRG_ISP_SEC_RSTDIS_REG, 0x0000002f); 200 /* clk enable */ 201 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 202 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 203 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 204 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 205 /* bus idle clear */ 206 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_ISP); 207 /* csi clk enable */ 208 mmio_write_32(CRG_PEREN3_REG, 0x00700000); 209 } 210 211 static void set_ivp_power_up(void) 212 { 213 /* set ivp ppll0 */ 214 mmio_write_32(CRG_CLKDIV0_REG, 0xc0000000); 215 /* set ivp 267MHz, 1600MHz / 6 */ 216 mmio_write_32(CRG_CLKDIV0_REG, 0x3c001400); 217 /* mtcmos on */ 218 mmio_write_32(CRG_PERPWREN_REG, 0x00200000); 219 udelay(100); 220 /* IVP CRG unreset */ 221 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000001); 222 /* clk enable */ 223 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 224 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 225 udelay(1); 226 /* clk disable */ 227 mmio_write_32(CRG_PERDIS4_REG, 0x000000a8); 228 mmio_write_32(CRG_CLKDIV20_REG, 0x02000000); 229 udelay(1); 230 /* iso disable */ 231 mmio_write_32(CRG_ISODIS_REG, 0x01000000); 232 /* unreset */ 233 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000002); 234 /* clk enable */ 235 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 236 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 237 /* bus idle clear */ 238 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_IVP); 239 /* set ivp 533MHz, 1600MHz / 3 */ 240 mmio_write_32(CRG_CLKDIV0_REG, 0x3c000800); 241 } 242 243 static void set_audio_power_up(void) 244 { 245 unsigned int ret; 246 int timeout = 100; 247 /* mtcmos on */ 248 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000001); 249 udelay(100); 250 /* clk enable */ 251 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 252 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 253 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 254 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 255 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 256 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 257 udelay(1); 258 /* clk disable */ 259 mmio_write_32(SCTRL_SCPERDIS1_REG, 0x0000000f); 260 mmio_write_32(SCTRL_SCPERDIS0_REG, 0x0c000000); 261 mmio_write_32(CRG_PERDIS5_REG, 0x00000080); 262 mmio_write_32(CRG_PERDIS0_REG, 0x04000000); 263 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010000); 264 mmio_write_32(CRG_CLKDIV19_REG, 0x80100000); 265 udelay(1); 266 /* iso disable */ 267 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000001); 268 udelay(1); 269 /* unreset */ 270 mmio_write_32(SCTRL_PERRSTDIS1_SEC_REG, 0x00000001); 271 mmio_write_32(SCTRL_SCPERRSTDIS0_REG, 0x00000780); 272 /* clk enable */ 273 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 274 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 275 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 276 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 277 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 278 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 279 /* bus idle clear */ 280 mmio_write_32(SCTRL_SCPERCTRL7_REG, 0x00040000); 281 for (;;) { 282 ret = mmio_read_32(SCTRL_SCPERSTAT6_REG); 283 if (((ret & (1 << 5)) == 0) && ((ret & (1 << 8)) == 0)) 284 break; 285 udelay(1); 286 timeout--; 287 if (timeout <= 0) { 288 WARN("%s timeout\n", __func__); 289 break; 290 } 291 } 292 mmio_write_32(ASP_CFG_MMBUF_CTRL_REG, 0x00ff0000); 293 } 294 295 static void set_pcie_power_up(void) 296 { 297 /* mtcmos on */ 298 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000010); 299 udelay(100); 300 /* clk enable */ 301 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 302 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 303 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 304 udelay(1); 305 /* clk disable */ 306 mmio_write_32(SCTRL_SCPERDIS2_REG, 0x00104000); 307 mmio_write_32(CRG_PERDIS7_REG, 0x000003a0); 308 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000000); 309 udelay(1); 310 /* iso disable */ 311 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000030); 312 /* unreset */ 313 mmio_write_32(CRG_PERRSTDIS3_REG, 0x8c000000); 314 /* clk enable */ 315 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 316 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 317 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 318 } 319 320 static void ispfunc_enable(void) 321 { 322 /* enable ispfunc. Otherwise powerup isp_srt causes exception. */ 323 mmio_write_32(0xfff35000, 0x00000008); 324 mmio_write_32(0xfff35460, 0xc004ffff); 325 mmio_write_32(0xfff35030, 0x02000000); 326 mdelay(10); 327 } 328 329 static void isps_control_clock(int flag) 330 { 331 unsigned int ret; 332 333 /* flag: 0 -- disable clock, 1 -- enable clock */ 334 if (flag) { 335 ret = mmio_read_32(0xe8420364); 336 ret |= 1; 337 mmio_write_32(0xe8420364, ret); 338 } else { 339 ret = mmio_read_32(0xe8420364); 340 ret &= ~1; 341 mmio_write_32(0xe8420364, ret); 342 } 343 } 344 345 static void set_isp_srt_power_up(void) 346 { 347 unsigned int ret; 348 349 ispfunc_enable(); 350 /* reset */ 351 mmio_write_32(0xe8420374, 0x00000001); 352 mmio_write_32(0xe8420350, 0x00000000); 353 mmio_write_32(0xe8420358, 0x00000000); 354 /* mtcmos on */ 355 mmio_write_32(0xfff35150, 0x00400000); 356 udelay(100); 357 /* clk enable */ 358 isps_control_clock(1); 359 udelay(1); 360 isps_control_clock(0); 361 udelay(1); 362 /* iso disable */ 363 mmio_write_32(0xfff35148, 0x08000000); 364 /* unreset */ 365 ret = mmio_read_32(0xe8420374); 366 ret &= ~0x1; 367 mmio_write_32(0xe8420374, ret); 368 /* clk enable */ 369 isps_control_clock(1); 370 /* enable clock gating for accessing csi registers */ 371 mmio_write_32(0xe8420010, ~0); 372 } 373 374 void hikey960_regulator_enable(void) 375 { 376 set_vivobus_power_up(); 377 hikey960_enable_ppll3(); 378 set_dss_power_up(); 379 set_vcodec_power_up(); 380 set_vdec_power_up(); 381 set_venc_power_up(); 382 set_isp_power_up(); 383 set_ivp_power_up(); 384 set_audio_power_up(); 385 set_pcie_power_up(); 386 set_isp_srt_power_up(); 387 388 /* set ISP_CORE_CTRL_S to unsecure mode */ 389 mmio_write_32(0xe8583800, 0x7); 390 /* set ISP_SUB_CTRL_S to unsecure mode */ 391 mmio_write_32(0xe8583804, 0xf); 392 } 393 394 void hikey960_tzc_init(void) 395 { 396 mmio_write_32(TZC_EN0_REG, 0x7fbff066); 397 mmio_write_32(TZC_EN1_REG, 0xfffff5fc); 398 mmio_write_32(TZC_EN2_REG, 0x0007005c); 399 mmio_write_32(TZC_EN3_REG, 0x37030700); 400 mmio_write_32(TZC_EN4_REG, 0xf63fefae); 401 mmio_write_32(TZC_EN5_REG, 0x000410fd); 402 mmio_write_32(TZC_EN6_REG, 0x0063ff68); 403 mmio_write_32(TZC_EN7_REG, 0x030000f3); 404 mmio_write_32(TZC_EN8_REG, 0x00000007); 405 } 406 407 void hikey960_peri_init(void) 408 { 409 /* unreset */ 410 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1); 411 } 412 413 void hikey960_pinmux_init(void) 414 { 415 unsigned int id; 416 417 hikey960_read_boardid(&id); 418 if (id == 5301) { 419 /* hikey960 hardware v2 */ 420 /* GPIO150: LED */ 421 mmio_write_32(IOMG_FIX_006_REG, 0); 422 /* GPIO151: LED */ 423 mmio_write_32(IOMG_FIX_007_REG, 0); 424 /* GPIO189: LED */ 425 mmio_write_32(IOMG_AO_011_REG, 0); 426 /* GPIO190: LED */ 427 mmio_write_32(IOMG_AO_012_REG, 0); 428 /* GPIO46 */ 429 mmio_write_32(IOMG_044_REG, 0); 430 /* GPIO202 */ 431 mmio_write_32(IOMG_AO_023_REG, 0); 432 /* GPIO206 */ 433 mmio_write_32(IOMG_AO_026_REG, 0); 434 /* GPIO219 - PD pullup */ 435 mmio_write_32(IOMG_AO_039_REG, 0); 436 mmio_write_32(IOCG_AO_043_REG, 1 << 0); 437 } 438 /* GPIO005 - PMU SSI, 10mA */ 439 mmio_write_32(IOCG_006_REG, 2 << 4); 440 /* GPIO213 - PCIE_CLKREQ_N */ 441 mmio_write_32(IOMG_AO_033_REG, 1); 442 } 443 444 void hikey960_gpio_init(void) 445 { 446 pl061_gpio_init(); 447 pl061_gpio_register(GPIO0_BASE, 0); 448 pl061_gpio_register(GPIO1_BASE, 1); 449 pl061_gpio_register(GPIO2_BASE, 2); 450 pl061_gpio_register(GPIO3_BASE, 3); 451 pl061_gpio_register(GPIO4_BASE, 4); 452 pl061_gpio_register(GPIO5_BASE, 5); 453 pl061_gpio_register(GPIO6_BASE, 6); 454 pl061_gpio_register(GPIO7_BASE, 7); 455 pl061_gpio_register(GPIO8_BASE, 8); 456 pl061_gpio_register(GPIO9_BASE, 9); 457 pl061_gpio_register(GPIO10_BASE, 10); 458 pl061_gpio_register(GPIO11_BASE, 11); 459 pl061_gpio_register(GPIO12_BASE, 12); 460 pl061_gpio_register(GPIO13_BASE, 13); 461 pl061_gpio_register(GPIO14_BASE, 14); 462 pl061_gpio_register(GPIO15_BASE, 15); 463 pl061_gpio_register(GPIO16_BASE, 16); 464 pl061_gpio_register(GPIO17_BASE, 17); 465 pl061_gpio_register(GPIO18_BASE, 18); 466 pl061_gpio_register(GPIO19_BASE, 19); 467 pl061_gpio_register(GPIO20_BASE, 20); 468 pl061_gpio_register(GPIO21_BASE, 21); 469 pl061_gpio_register(GPIO22_BASE, 22); 470 pl061_gpio_register(GPIO23_BASE, 23); 471 pl061_gpio_register(GPIO24_BASE, 24); 472 pl061_gpio_register(GPIO25_BASE, 25); 473 pl061_gpio_register(GPIO26_BASE, 26); 474 pl061_gpio_register(GPIO27_BASE, 27); 475 pl061_gpio_register(GPIO28_BASE, 28); 476 477 /* PCIE_PERST_N output low */ 478 gpio_set_direction(89, GPIO_DIR_OUT); 479 gpio_set_value(89, GPIO_LEVEL_LOW); 480 } 481