1 /* 2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <bl31/interrupt_mgmt.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/interrupt_props.h> 17 #include <drivers/arm/cci.h> 18 #include <drivers/arm/gicv2.h> 19 #include <drivers/arm/pl011.h> 20 #include <drivers/console.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <lib/mmio.h> 23 #include <lib/xlat_tables/xlat_tables_v2.h> 24 #include <plat/common/platform.h> 25 #include <services/el3_spmc_ffa_memory.h> 26 27 #include <hi3660.h> 28 #include <hisi_ipc.h> 29 #include "hikey960_def.h" 30 #include "hikey960_private.h" 31 32 static entry_point_info_t bl32_ep_info; 33 static entry_point_info_t bl33_ep_info; 34 static console_t console; 35 36 /* fastboot serial number consumed by Kinibi SPD/LP for gpd.tee.deviceID. */ 37 uint64_t fastboot_serno; 38 39 /****************************************************************************** 40 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 41 * interrupts. 42 *****************************************************************************/ 43 static const interrupt_prop_t g0_interrupt_props[] = { 44 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 45 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 46 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 47 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 48 }; 49 50 const gicv2_driver_data_t hikey960_gic_data = { 51 .gicd_base = GICD_REG_BASE, 52 .gicc_base = GICC_REG_BASE, 53 .interrupt_props = g0_interrupt_props, 54 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 55 }; 56 57 static const int cci_map[] = { 58 CCI400_SL_IFACE3_CLUSTER_IX, 59 CCI400_SL_IFACE4_CLUSTER_IX 60 }; 61 62 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 63 { 64 entry_point_info_t *next_image_info; 65 66 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 67 68 /* None of the images on this platform can have 0x0 as the entrypoint */ 69 if (next_image_info->pc) 70 return next_image_info; 71 return NULL; 72 } 73 74 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 75 u_register_t arg2, u_register_t arg3) 76 { 77 unsigned int id, uart_base; 78 void *from_bl2; 79 plat_params_from_bl2_t *plat_params_from_bl2 = (plat_params_from_bl2_t *) arg1; 80 81 from_bl2 = (void *) arg0; 82 83 generic_delay_timer_init(); 84 hikey960_read_boardid(&id); 85 if (id == 5300) 86 uart_base = PL011_UART5_BASE; 87 else 88 uart_base = PL011_UART6_BASE; 89 90 /* Initialize the console to provide early debug support */ 91 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 92 PL011_BAUDRATE, &console); 93 94 /* Initialize CCI driver */ 95 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); 96 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 97 98 /* Fastboot serial number passed from BL2 as a platform parameter */ 99 fastboot_serno = plat_params_from_bl2->fastboot_serno; 100 INFO("BL31: fastboot_serno %lx\n", fastboot_serno); 101 102 /* 103 * Check params passed from BL2 should not be NULL, 104 */ 105 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 106 assert(params_from_bl2 != NULL); 107 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 108 assert(params_from_bl2->h.version >= VERSION_2); 109 110 bl_params_node_t *bl_params = params_from_bl2->head; 111 112 /* 113 * Copy BL33 and BL32 (if present), entry point information. 114 * They are stored in Secure RAM, in BL2's address space. 115 */ 116 while (bl_params) { 117 if (bl_params->image_id == BL32_IMAGE_ID) 118 bl32_ep_info = *bl_params->ep_info; 119 120 if (bl_params->image_id == BL33_IMAGE_ID) 121 bl33_ep_info = *bl_params->ep_info; 122 123 bl_params = bl_params->next_params_info; 124 } 125 126 if (bl33_ep_info.pc == 0) 127 panic(); 128 } 129 130 void bl31_plat_arch_setup(void) 131 { 132 #if SPMC_AT_EL3 133 mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE, 134 MT_MEMORY | MT_RW | MT_SECURE); 135 #endif 136 137 hikey960_init_mmu_el3(BL31_BASE, 138 BL31_LIMIT - BL31_BASE, 139 BL_CODE_BASE, 140 BL_CODE_END, 141 BL_COHERENT_RAM_BASE, 142 BL_COHERENT_RAM_END); 143 } 144 145 static void hikey960_edma_init(void) 146 { 147 int i; 148 uint32_t non_secure; 149 150 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 151 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 152 153 /* Channel 0 is reserved for LPM3, keep secure */ 154 for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) { 155 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 156 } 157 } 158 159 static void hikey960_iomcu_dma_init(void) 160 { 161 int i; 162 uint32_t non_secure; 163 164 non_secure = IOMCU_DMAC_SEC_CTRL_INTR_SEC | IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC; 165 mmio_write_32(IOMCU_DMAC_SEC_CTRL, non_secure); 166 167 /* channels 0-3 are reserved */ 168 for (i = 4; i < IOMCU_DMAC_CHANNEL_NUMS; i++) { 169 mmio_write_32(IOMCU_DMAC_AXI_CONF(i), IOMCU_DMAC_AXI_CONF_ARPROT_NS | 170 IOMCU_DMAC_AXI_CONF_AWPROT_NS); 171 } 172 } 173 174 #if SPMC_AT_EL3 175 /* 176 * On the hikey960 platform when using the EL3 SPMC implementation allocate the 177 * datastore for tracking shared memory descriptors in the RAM2 DRAM section 178 * to ensure sufficient storage can be allocated. 179 * Provide an implementation of the accessor method to allow the datastore 180 * details to be retrieved by the SPMC. 181 * The SPMC will take care of initializing the memory region. 182 */ 183 184 #define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024) 185 186 __section(".ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE]; 187 188 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 189 { 190 *datastore = plat_spmc_shmem_datastore; 191 *size = SPMC_SHARED_MEMORY_OBJ_SIZE; 192 return 0; 193 } 194 195 /* 196 * Add dummy implementations of memory management related platform hooks. 197 * These can be used to implement platform specific functionality to support 198 * a memory sharing/lending operation. 199 * 200 * Note: The hooks must be located as part of the initial share request and 201 * final reclaim to prevent order dependencies with operations that may take 202 * place in the normal world without visibility of the SPMC. 203 */ 204 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 205 { 206 return 0; 207 } 208 209 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 210 { 211 return 0; 212 } 213 214 #endif 215 216 void bl31_platform_setup(void) 217 { 218 /* Initialize the GIC driver, cpu and distributor interfaces */ 219 gicv2_driver_init(&hikey960_gic_data); 220 gicv2_distif_init(); 221 gicv2_pcpu_distif_init(); 222 gicv2_cpuif_enable(); 223 224 hikey960_edma_init(); 225 hikey960_iomcu_dma_init(); 226 hikey960_gpio_init(); 227 228 hisi_ipc_init(); 229 } 230 231 #ifdef SPD_none 232 static uint64_t hikey_debug_fiq_handler(uint32_t id, 233 uint32_t flags, 234 void *handle, 235 void *cookie) 236 { 237 int intr, intr_raw; 238 239 /* Acknowledge interrupt */ 240 intr_raw = plat_ic_acknowledge_interrupt(); 241 intr = plat_ic_get_interrupt_id(intr_raw); 242 ERROR("Invalid interrupt: intr=%d\n", intr); 243 console_flush(); 244 panic(); 245 246 return 0; 247 } 248 #elif defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 249 /* 250 * A dummy implementation of the platform handler for Group0 secure interrupt. 251 */ 252 int plat_spmd_handle_group0_interrupt(uint32_t intid) 253 { 254 (void)intid; 255 return -1; 256 } 257 #endif 258 259 void bl31_plat_runtime_setup(void) 260 { 261 #ifdef SPD_none 262 uint32_t flags; 263 int32_t rc; 264 265 flags = 0; 266 set_interrupt_rm_flag(flags, NON_SECURE); 267 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 268 hikey_debug_fiq_handler, 269 flags); 270 if (rc != 0) 271 panic(); 272 #endif 273 } 274