1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <errno.h> 14 #include <generic_delay_timer.h> 15 #include <gicv2.h> 16 #include <hi3660.h> 17 #include <hisi_ipc.h> 18 #include <interrupt_mgmt.h> 19 #include <interrupt_props.h> 20 #include <pl011.h> 21 #include <platform.h> 22 #include <platform_def.h> 23 24 #include "hikey960_def.h" 25 #include "hikey960_private.h" 26 27 /* 28 * The next 2 constants identify the extents of the code & RO data region. 29 * These addresses are used by the MMU setup code and therefore they must be 30 * page-aligned. It is the responsibility of the linker script to ensure that 31 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 32 */ 33 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 34 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 35 36 /* 37 * The next 2 constants identify the extents of the coherent memory region. 38 * These addresses are used by the MMU setup code and therefore they must be 39 * page-aligned. It is the responsibility of the linker script to ensure that 40 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 41 * page-aligned addresses. 42 */ 43 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 44 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 45 46 static entry_point_info_t bl32_ep_info; 47 static entry_point_info_t bl33_ep_info; 48 static console_pl011_t console; 49 50 /****************************************************************************** 51 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 52 * interrupts. 53 *****************************************************************************/ 54 static const interrupt_prop_t g0_interrupt_props[] = { 55 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 56 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 57 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 58 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 59 }; 60 61 const gicv2_driver_data_t hikey960_gic_data = { 62 .gicd_base = GICD_REG_BASE, 63 .gicc_base = GICC_REG_BASE, 64 .interrupt_props = g0_interrupt_props, 65 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 66 }; 67 68 static const int cci_map[] = { 69 CCI400_SL_IFACE3_CLUSTER_IX, 70 CCI400_SL_IFACE4_CLUSTER_IX 71 }; 72 73 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 74 { 75 entry_point_info_t *next_image_info; 76 77 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 78 79 /* None of the images on this platform can have 0x0 as the entrypoint */ 80 if (next_image_info->pc) 81 return next_image_info; 82 return NULL; 83 } 84 85 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 86 u_register_t arg2, u_register_t arg3) 87 { 88 unsigned int id, uart_base; 89 void *from_bl2; 90 91 from_bl2 = (void *) arg0; 92 93 generic_delay_timer_init(); 94 hikey960_read_boardid(&id); 95 if (id == 5300) 96 uart_base = PL011_UART5_BASE; 97 else 98 uart_base = PL011_UART6_BASE; 99 100 /* Initialize the console to provide early debug support */ 101 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 102 PL011_BAUDRATE, &console); 103 104 /* Initialize CCI driver */ 105 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); 106 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 107 108 /* 109 * Check params passed from BL2 should not be NULL, 110 */ 111 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 112 assert(params_from_bl2 != NULL); 113 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 114 assert(params_from_bl2->h.version >= VERSION_2); 115 116 bl_params_node_t *bl_params = params_from_bl2->head; 117 118 /* 119 * Copy BL33 and BL32 (if present), entry point information. 120 * They are stored in Secure RAM, in BL2's address space. 121 */ 122 while (bl_params) { 123 if (bl_params->image_id == BL32_IMAGE_ID) 124 bl32_ep_info = *bl_params->ep_info; 125 126 if (bl_params->image_id == BL33_IMAGE_ID) 127 bl33_ep_info = *bl_params->ep_info; 128 129 bl_params = bl_params->next_params_info; 130 } 131 132 if (bl33_ep_info.pc == 0) 133 panic(); 134 } 135 136 void bl31_plat_arch_setup(void) 137 { 138 hikey960_init_mmu_el3(BL31_BASE, 139 BL31_LIMIT - BL31_BASE, 140 BL31_RO_BASE, 141 BL31_RO_LIMIT, 142 BL31_COHERENT_RAM_BASE, 143 BL31_COHERENT_RAM_LIMIT); 144 } 145 146 void bl31_platform_setup(void) 147 { 148 /* Initialize the GIC driver, cpu and distributor interfaces */ 149 gicv2_driver_init(&hikey960_gic_data); 150 gicv2_distif_init(); 151 gicv2_pcpu_distif_init(); 152 gicv2_cpuif_enable(); 153 154 hisi_ipc_init(); 155 } 156 157 #ifdef SPD_none 158 static uint64_t hikey_debug_fiq_handler(uint32_t id, 159 uint32_t flags, 160 void *handle, 161 void *cookie) 162 { 163 int intr, intr_raw; 164 165 /* Acknowledge interrupt */ 166 intr_raw = plat_ic_acknowledge_interrupt(); 167 intr = plat_ic_get_interrupt_id(intr_raw); 168 ERROR("Invalid interrupt: intr=%d\n", intr); 169 console_flush(); 170 panic(); 171 172 return 0; 173 } 174 #endif 175 176 void bl31_plat_runtime_setup(void) 177 { 178 #ifdef SPD_none 179 uint32_t flags; 180 int32_t rc; 181 182 flags = 0; 183 set_interrupt_rm_flag(flags, NON_SECURE); 184 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 185 hikey_debug_fiq_handler, 186 flags); 187 if (rc != 0) 188 panic(); 189 #endif 190 } 191