1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <bl31/interrupt_mgmt.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/interrupt_props.h> 17 #include <drivers/arm/cci.h> 18 #include <drivers/arm/gicv2.h> 19 #include <drivers/arm/pl011.h> 20 #include <drivers/console.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <lib/mmio.h> 23 #include <plat/common/platform.h> 24 25 #include <hi3660.h> 26 #include <hisi_ipc.h> 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 static entry_point_info_t bl32_ep_info; 31 static entry_point_info_t bl33_ep_info; 32 static console_pl011_t console; 33 34 /****************************************************************************** 35 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 36 * interrupts. 37 *****************************************************************************/ 38 static const interrupt_prop_t g0_interrupt_props[] = { 39 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 41 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 42 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 43 }; 44 45 const gicv2_driver_data_t hikey960_gic_data = { 46 .gicd_base = GICD_REG_BASE, 47 .gicc_base = GICC_REG_BASE, 48 .interrupt_props = g0_interrupt_props, 49 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 50 }; 51 52 static const int cci_map[] = { 53 CCI400_SL_IFACE3_CLUSTER_IX, 54 CCI400_SL_IFACE4_CLUSTER_IX 55 }; 56 57 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 58 { 59 entry_point_info_t *next_image_info; 60 61 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 62 63 /* None of the images on this platform can have 0x0 as the entrypoint */ 64 if (next_image_info->pc) 65 return next_image_info; 66 return NULL; 67 } 68 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 unsigned int id, uart_base; 73 void *from_bl2; 74 75 from_bl2 = (void *) arg0; 76 77 generic_delay_timer_init(); 78 hikey960_read_boardid(&id); 79 if (id == 5300) 80 uart_base = PL011_UART5_BASE; 81 else 82 uart_base = PL011_UART6_BASE; 83 84 /* Initialize the console to provide early debug support */ 85 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 86 PL011_BAUDRATE, &console); 87 88 /* Initialize CCI driver */ 89 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); 90 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 91 92 /* 93 * Check params passed from BL2 should not be NULL, 94 */ 95 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 96 assert(params_from_bl2 != NULL); 97 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 98 assert(params_from_bl2->h.version >= VERSION_2); 99 100 bl_params_node_t *bl_params = params_from_bl2->head; 101 102 /* 103 * Copy BL33 and BL32 (if present), entry point information. 104 * They are stored in Secure RAM, in BL2's address space. 105 */ 106 while (bl_params) { 107 if (bl_params->image_id == BL32_IMAGE_ID) 108 bl32_ep_info = *bl_params->ep_info; 109 110 if (bl_params->image_id == BL33_IMAGE_ID) 111 bl33_ep_info = *bl_params->ep_info; 112 113 bl_params = bl_params->next_params_info; 114 } 115 116 if (bl33_ep_info.pc == 0) 117 panic(); 118 } 119 120 void bl31_plat_arch_setup(void) 121 { 122 hikey960_init_mmu_el3(BL31_BASE, 123 BL31_LIMIT - BL31_BASE, 124 BL_CODE_BASE, 125 BL_CODE_END, 126 BL_COHERENT_RAM_BASE, 127 BL_COHERENT_RAM_END); 128 } 129 130 static void hikey960_edma_init(void) 131 { 132 int i; 133 uint32_t non_secure; 134 135 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 136 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 137 138 /* Channel 0 is reserved for LPM3, keep secure */ 139 for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) { 140 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 141 } 142 } 143 144 void bl31_platform_setup(void) 145 { 146 /* Initialize the GIC driver, cpu and distributor interfaces */ 147 gicv2_driver_init(&hikey960_gic_data); 148 gicv2_distif_init(); 149 gicv2_pcpu_distif_init(); 150 gicv2_cpuif_enable(); 151 152 hikey960_edma_init(); 153 154 hisi_ipc_init(); 155 } 156 157 #ifdef SPD_none 158 static uint64_t hikey_debug_fiq_handler(uint32_t id, 159 uint32_t flags, 160 void *handle, 161 void *cookie) 162 { 163 int intr, intr_raw; 164 165 /* Acknowledge interrupt */ 166 intr_raw = plat_ic_acknowledge_interrupt(); 167 intr = plat_ic_get_interrupt_id(intr_raw); 168 ERROR("Invalid interrupt: intr=%d\n", intr); 169 console_flush(); 170 panic(); 171 172 return 0; 173 } 174 #endif 175 176 void bl31_plat_runtime_setup(void) 177 { 178 #ifdef SPD_none 179 uint32_t flags; 180 int32_t rc; 181 182 flags = 0; 183 set_interrupt_rm_flag(flags, NON_SECURE); 184 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 185 hikey_debug_fiq_handler, 186 flags); 187 if (rc != 0) 188 panic(); 189 #endif 190 } 191