1 /* 2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <bl31/interrupt_mgmt.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/interrupt_props.h> 17 #include <drivers/arm/cci.h> 18 #include <drivers/arm/gicv2.h> 19 #include <drivers/arm/pl011.h> 20 #include <drivers/console.h> 21 #include <drivers/generic_delay_timer.h> 22 #include <lib/mmio.h> 23 #include <lib/xlat_tables/xlat_tables_v2.h> 24 #include <plat/common/platform.h> 25 #include <services/el3_spmc_ffa_memory.h> 26 27 #include <hi3660.h> 28 #include <hisi_ipc.h> 29 #include "hikey960_def.h" 30 #include "hikey960_private.h" 31 32 static entry_point_info_t bl32_ep_info; 33 static entry_point_info_t bl33_ep_info; 34 static console_t console; 35 36 /****************************************************************************** 37 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 38 * interrupts. 39 *****************************************************************************/ 40 static const interrupt_prop_t g0_interrupt_props[] = { 41 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 42 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 43 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 44 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 45 }; 46 47 const gicv2_driver_data_t hikey960_gic_data = { 48 .gicd_base = GICD_REG_BASE, 49 .gicc_base = GICC_REG_BASE, 50 .interrupt_props = g0_interrupt_props, 51 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 52 }; 53 54 static const int cci_map[] = { 55 CCI400_SL_IFACE3_CLUSTER_IX, 56 CCI400_SL_IFACE4_CLUSTER_IX 57 }; 58 59 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 60 { 61 entry_point_info_t *next_image_info; 62 63 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 64 65 /* None of the images on this platform can have 0x0 as the entrypoint */ 66 if (next_image_info->pc) 67 return next_image_info; 68 return NULL; 69 } 70 71 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 72 u_register_t arg2, u_register_t arg3) 73 { 74 unsigned int id, uart_base; 75 void *from_bl2; 76 77 from_bl2 = (void *) arg0; 78 79 generic_delay_timer_init(); 80 hikey960_read_boardid(&id); 81 if (id == 5300) 82 uart_base = PL011_UART5_BASE; 83 else 84 uart_base = PL011_UART6_BASE; 85 86 /* Initialize the console to provide early debug support */ 87 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 88 PL011_BAUDRATE, &console); 89 90 /* Initialize CCI driver */ 91 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); 92 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 93 94 /* 95 * Check params passed from BL2 should not be NULL, 96 */ 97 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 98 assert(params_from_bl2 != NULL); 99 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 100 assert(params_from_bl2->h.version >= VERSION_2); 101 102 bl_params_node_t *bl_params = params_from_bl2->head; 103 104 /* 105 * Copy BL33 and BL32 (if present), entry point information. 106 * They are stored in Secure RAM, in BL2's address space. 107 */ 108 while (bl_params) { 109 if (bl_params->image_id == BL32_IMAGE_ID) 110 bl32_ep_info = *bl_params->ep_info; 111 112 if (bl_params->image_id == BL33_IMAGE_ID) 113 bl33_ep_info = *bl_params->ep_info; 114 115 bl_params = bl_params->next_params_info; 116 } 117 118 if (bl33_ep_info.pc == 0) 119 panic(); 120 } 121 122 void bl31_plat_arch_setup(void) 123 { 124 #if SPMC_AT_EL3 125 mmap_add_region(DDR2_SEC_BASE, DDR2_SEC_BASE, DDR2_SEC_SIZE, 126 MT_MEMORY | MT_RW | MT_SECURE); 127 #endif 128 129 hikey960_init_mmu_el3(BL31_BASE, 130 BL31_LIMIT - BL31_BASE, 131 BL_CODE_BASE, 132 BL_CODE_END, 133 BL_COHERENT_RAM_BASE, 134 BL_COHERENT_RAM_END); 135 } 136 137 static void hikey960_edma_init(void) 138 { 139 int i; 140 uint32_t non_secure; 141 142 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 143 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 144 145 /* Channel 0 is reserved for LPM3, keep secure */ 146 for (i = 1; i < EDMAC_CHANNEL_NUMS; i++) { 147 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 148 } 149 } 150 151 static void hikey960_iomcu_dma_init(void) 152 { 153 int i; 154 uint32_t non_secure; 155 156 non_secure = IOMCU_DMAC_SEC_CTRL_INTR_SEC | IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC; 157 mmio_write_32(IOMCU_DMAC_SEC_CTRL, non_secure); 158 159 /* channels 0-3 are reserved */ 160 for (i = 4; i < IOMCU_DMAC_CHANNEL_NUMS; i++) { 161 mmio_write_32(IOMCU_DMAC_AXI_CONF(i), IOMCU_DMAC_AXI_CONF_ARPROT_NS | 162 IOMCU_DMAC_AXI_CONF_AWPROT_NS); 163 } 164 } 165 166 #if SPMC_AT_EL3 167 /* 168 * On the hikey960 platform when using the EL3 SPMC implementation allocate the 169 * datastore for tracking shared memory descriptors in the RAM2 DRAM section 170 * to ensure sufficient storage can be allocated. 171 * Provide an implementation of the accessor method to allow the datastore 172 * details to be retrieved by the SPMC. 173 * The SPMC will take care of initializing the memory region. 174 */ 175 176 #define SPMC_SHARED_MEMORY_OBJ_SIZE (512 * 1024) 177 178 __section("ram2_region") uint8_t plat_spmc_shmem_datastore[SPMC_SHARED_MEMORY_OBJ_SIZE]; 179 180 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 181 { 182 *datastore = plat_spmc_shmem_datastore; 183 *size = SPMC_SHARED_MEMORY_OBJ_SIZE; 184 return 0; 185 } 186 187 /* 188 * Add dummy implementations of memory management related platform hooks. 189 * These can be used to implement platform specific functionality to support 190 * a memory sharing/lending operation. 191 * 192 * Note: The hooks must be located as part of the initial share request and 193 * final reclaim to prevent order dependencies with operations that may take 194 * place in the normal world without visibility of the SPMC. 195 */ 196 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 197 { 198 return 0; 199 } 200 201 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 202 { 203 return 0; 204 } 205 206 #endif 207 208 void bl31_platform_setup(void) 209 { 210 /* Initialize the GIC driver, cpu and distributor interfaces */ 211 gicv2_driver_init(&hikey960_gic_data); 212 gicv2_distif_init(); 213 gicv2_pcpu_distif_init(); 214 gicv2_cpuif_enable(); 215 216 hikey960_edma_init(); 217 hikey960_iomcu_dma_init(); 218 hikey960_gpio_init(); 219 220 hisi_ipc_init(); 221 } 222 223 #ifdef SPD_none 224 static uint64_t hikey_debug_fiq_handler(uint32_t id, 225 uint32_t flags, 226 void *handle, 227 void *cookie) 228 { 229 int intr, intr_raw; 230 231 /* Acknowledge interrupt */ 232 intr_raw = plat_ic_acknowledge_interrupt(); 233 intr = plat_ic_get_interrupt_id(intr_raw); 234 ERROR("Invalid interrupt: intr=%d\n", intr); 235 console_flush(); 236 panic(); 237 238 return 0; 239 } 240 #endif 241 242 void bl31_plat_runtime_setup(void) 243 { 244 #ifdef SPD_none 245 uint32_t flags; 246 int32_t rc; 247 248 flags = 0; 249 set_interrupt_rm_flag(flags, NON_SECURE); 250 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 251 hikey_debug_fiq_handler, 252 flags); 253 if (rc != 0) 254 panic(); 255 #endif 256 } 257