1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/dw_ufs.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/ufs.h> 22 #include <lib/mmio.h> 23 #ifdef SPD_opteed 24 #include <lib/optee_utils.h> 25 #endif 26 27 #include <hi3660.h> 28 #include "hikey960_def.h" 29 #include "hikey960_private.h" 30 31 #define BL2_RW_BASE (BL_CODE_END) 32 33 static meminfo_t bl2_el3_tzram_layout; 34 static console_pl011_t console; 35 extern int load_lpm3(void); 36 37 enum { 38 BOOT_MODE_RECOVERY = 0, 39 BOOT_MODE_NORMAL, 40 BOOT_MODE_MASK = 1, 41 }; 42 43 /******************************************************************************* 44 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 45 * Return 0 on success, -1 otherwise. 46 ******************************************************************************/ 47 int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 48 { 49 int i; 50 int *buf; 51 52 assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE); 53 54 INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); 55 56 INFO("BL2: SCP_BL2: 0x%lx@0x%x\n", 57 scp_bl2_image_info->image_base, 58 scp_bl2_image_info->image_size); 59 60 buf = (int *)scp_bl2_image_info->image_base; 61 62 INFO("BL2: SCP_BL2 HEAD:\n"); 63 for (i = 0; i < 64; i += 4) 64 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 65 buf[i], buf[i+1], buf[i+2], buf[i+3]); 66 67 buf = (int *)(scp_bl2_image_info->image_base + 68 scp_bl2_image_info->image_size - 256); 69 70 INFO("BL2: SCP_BL2 TAIL:\n"); 71 for (i = 0; i < 64; i += 4) 72 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 73 buf[i], buf[i+1], buf[i+2], buf[i+3]); 74 75 INFO("BL2: SCP_BL2 transferred to SCP\n"); 76 77 load_lpm3(); 78 (void)buf; 79 80 return 0; 81 } 82 83 static void hikey960_ufs_reset(void) 84 { 85 unsigned int data, mask; 86 87 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 88 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 89 do { 90 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 91 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 92 /* use abb clk */ 93 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 94 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 95 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 96 mdelay(1); 97 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 98 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 99 100 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 101 do { 102 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 103 } while ((data & PERI_UFS_BIT) == 0); 104 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 105 mdelay(1); 106 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 107 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 108 MASK_UFS_DEVICE_RESET); 109 /* clear SC_DIV_UFS_PERIBUS */ 110 mask = SC_DIV_UFS_PERIBUS << 16; 111 mmio_write_32(CRG_CLKDIV17_REG, mask); 112 /* set SC_DIV_UFSPHY_CFG(3) */ 113 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 114 data = SC_DIV_UFSPHY_CFG(3); 115 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 116 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 117 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 118 data |= 0x39; 119 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 120 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 121 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 122 MASK_UFS_CLK_GATE_BYPASS); 123 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 124 125 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 126 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 127 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 128 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 129 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 130 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 131 mdelay(1); 132 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 133 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 134 mdelay(20); 135 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 136 0x03300330); 137 138 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 139 do { 140 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 141 } while (data & PERI_UFS_BIT); 142 } 143 144 static void hikey960_init_ufs(void) 145 { 146 dw_ufs_params_t ufs_params; 147 148 memset(&ufs_params, 0, sizeof(ufs_params_t)); 149 ufs_params.reg_base = UFS_REG_BASE; 150 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 151 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 152 hikey960_ufs_reset(); 153 dw_ufs_init(&ufs_params); 154 } 155 156 /******************************************************************************* 157 * Gets SPSR for BL32 entry 158 ******************************************************************************/ 159 uint32_t hikey960_get_spsr_for_bl32_entry(void) 160 { 161 /* 162 * The Secure Payload Dispatcher service is responsible for 163 * setting the SPSR prior to entry into the BL3-2 image. 164 */ 165 return 0; 166 } 167 168 /******************************************************************************* 169 * Gets SPSR for BL33 entry 170 ******************************************************************************/ 171 #ifndef AARCH32 172 uint32_t hikey960_get_spsr_for_bl33_entry(void) 173 { 174 unsigned int mode; 175 uint32_t spsr; 176 177 /* Figure out what mode we enter the non-secure world in */ 178 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 179 180 /* 181 * TODO: Consider the possibility of specifying the SPSR in 182 * the FIP ToC and allowing the platform to have a say as 183 * well. 184 */ 185 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 186 return spsr; 187 } 188 #else 189 uint32_t hikey960_get_spsr_for_bl33_entry(void) 190 { 191 unsigned int hyp_status, mode, spsr; 192 193 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 194 195 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 196 197 /* 198 * TODO: Consider the possibility of specifying the SPSR in 199 * the FIP ToC and allowing the platform to have a say as 200 * well. 201 */ 202 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 203 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 204 return spsr; 205 } 206 #endif /* AARCH32 */ 207 208 int hikey960_bl2_handle_post_image_load(unsigned int image_id) 209 { 210 int err = 0; 211 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 212 #ifdef SPD_opteed 213 bl_mem_params_node_t *pager_mem_params = NULL; 214 bl_mem_params_node_t *paged_mem_params = NULL; 215 #endif 216 assert(bl_mem_params); 217 218 switch (image_id) { 219 #ifdef AARCH64 220 case BL32_IMAGE_ID: 221 #ifdef SPD_opteed 222 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 223 assert(pager_mem_params); 224 225 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 226 assert(paged_mem_params); 227 228 err = parse_optee_header(&bl_mem_params->ep_info, 229 &pager_mem_params->image_info, 230 &paged_mem_params->image_info); 231 if (err != 0) { 232 WARN("OPTEE header parse error.\n"); 233 } 234 #endif 235 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry(); 236 break; 237 #endif 238 239 case BL33_IMAGE_ID: 240 /* BL33 expects to receive the primary CPU MPID (through r0) */ 241 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 242 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry(); 243 break; 244 245 #ifdef SCP_BL2_BASE 246 case SCP_BL2_IMAGE_ID: 247 /* The subsequent handling of SCP_BL2 is platform specific */ 248 err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info); 249 if (err) { 250 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 251 } 252 break; 253 #endif 254 default: 255 /* Do nothing in default case */ 256 break; 257 } 258 259 return err; 260 } 261 262 /******************************************************************************* 263 * This function can be used by the platforms to update/use image 264 * information for given `image_id`. 265 ******************************************************************************/ 266 int bl2_plat_handle_post_image_load(unsigned int image_id) 267 { 268 return hikey960_bl2_handle_post_image_load(image_id); 269 } 270 271 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 272 u_register_t arg3, u_register_t arg4) 273 { 274 unsigned int id, uart_base; 275 276 generic_delay_timer_init(); 277 hikey960_read_boardid(&id); 278 if (id == 5300) 279 uart_base = PL011_UART5_BASE; 280 else 281 uart_base = PL011_UART6_BASE; 282 /* Initialize the console to provide early debug support */ 283 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 284 PL011_BAUDRATE, &console); 285 /* 286 * Allow BL2 to see the whole Trusted RAM. 287 */ 288 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 289 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 290 } 291 292 void bl2_el3_plat_arch_setup(void) 293 { 294 hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base, 295 bl2_el3_tzram_layout.total_size, 296 BL_CODE_BASE, 297 BL_CODE_END, 298 BL_COHERENT_RAM_BASE, 299 BL_COHERENT_RAM_END); 300 } 301 302 void bl2_platform_setup(void) 303 { 304 /* disable WDT0 */ 305 if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { 306 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); 307 mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0); 308 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0); 309 } 310 hikey960_clk_init(); 311 hikey960_pmu_init(); 312 hikey960_regulator_enable(); 313 hikey960_tzc_init(); 314 hikey960_peri_init(); 315 hikey960_pinmux_init(); 316 hikey960_gpio_init(); 317 hikey960_init_ufs(); 318 hikey960_io_setup(); 319 } 320