1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/dw_ufs.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/partition/partition.h> 22 #include <drivers/ufs.h> 23 #include <lib/mmio.h> 24 #ifdef SPD_opteed 25 #include <lib/optee_utils.h> 26 #endif 27 28 #include <hi3660.h> 29 #include "hikey960_def.h" 30 #include "hikey960_private.h" 31 32 #define BL2_RW_BASE (BL_CODE_END) 33 34 static meminfo_t bl2_el3_tzram_layout; 35 static console_t console; 36 extern int load_lpm3(void); 37 38 enum { 39 BOOT_MODE_RECOVERY = 0, 40 BOOT_MODE_NORMAL, 41 BOOT_MODE_MASK = 1, 42 }; 43 44 /******************************************************************************* 45 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 46 * Return 0 on success, -1 otherwise. 47 ******************************************************************************/ 48 int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 49 { 50 int i; 51 int *buf; 52 53 assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE); 54 55 INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); 56 57 INFO("BL2: SCP_BL2: 0x%lx@0x%x\n", 58 scp_bl2_image_info->image_base, 59 scp_bl2_image_info->image_size); 60 61 buf = (int *)scp_bl2_image_info->image_base; 62 63 INFO("BL2: SCP_BL2 HEAD:\n"); 64 for (i = 0; i < 64; i += 4) 65 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 66 buf[i], buf[i+1], buf[i+2], buf[i+3]); 67 68 buf = (int *)(scp_bl2_image_info->image_base + 69 scp_bl2_image_info->image_size - 256); 70 71 INFO("BL2: SCP_BL2 TAIL:\n"); 72 for (i = 0; i < 64; i += 4) 73 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 74 buf[i], buf[i+1], buf[i+2], buf[i+3]); 75 76 INFO("BL2: SCP_BL2 transferred to SCP\n"); 77 78 load_lpm3(); 79 (void)buf; 80 81 return 0; 82 } 83 84 static void hikey960_ufs_reset(void) 85 { 86 unsigned int data, mask; 87 88 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 89 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 90 do { 91 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 92 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 93 /* use abb clk */ 94 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 95 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 96 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 97 mdelay(1); 98 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 99 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 100 101 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 102 do { 103 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 104 } while ((data & PERI_UFS_BIT) == 0); 105 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 106 mdelay(1); 107 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 108 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 109 MASK_UFS_DEVICE_RESET); 110 /* clear SC_DIV_UFS_PERIBUS */ 111 mask = SC_DIV_UFS_PERIBUS << 16; 112 mmio_write_32(CRG_CLKDIV17_REG, mask); 113 /* set SC_DIV_UFSPHY_CFG(3) */ 114 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 115 data = SC_DIV_UFSPHY_CFG(3); 116 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 117 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 118 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 119 data |= 0x39; 120 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 121 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 122 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 123 MASK_UFS_CLK_GATE_BYPASS); 124 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 125 126 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 127 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 128 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 129 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 130 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 131 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 132 mdelay(1); 133 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 134 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 135 mdelay(20); 136 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 137 0x03300330); 138 139 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 140 do { 141 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 142 } while (data & PERI_UFS_BIT); 143 } 144 145 static void hikey960_init_ufs(void) 146 { 147 dw_ufs_params_t ufs_params; 148 149 memset(&ufs_params, 0, sizeof(ufs_params_t)); 150 ufs_params.reg_base = UFS_REG_BASE; 151 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 152 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 153 hikey960_ufs_reset(); 154 dw_ufs_init(&ufs_params); 155 } 156 157 /******************************************************************************* 158 * Gets SPSR for BL32 entry 159 ******************************************************************************/ 160 uint32_t hikey960_get_spsr_for_bl32_entry(void) 161 { 162 /* 163 * The Secure Payload Dispatcher service is responsible for 164 * setting the SPSR prior to entry into the BL3-2 image. 165 */ 166 return 0; 167 } 168 169 /******************************************************************************* 170 * Gets SPSR for BL33 entry 171 ******************************************************************************/ 172 #ifdef __aarch64__ 173 uint32_t hikey960_get_spsr_for_bl33_entry(void) 174 { 175 unsigned int mode; 176 uint32_t spsr; 177 178 /* Figure out what mode we enter the non-secure world in */ 179 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 180 181 /* 182 * TODO: Consider the possibility of specifying the SPSR in 183 * the FIP ToC and allowing the platform to have a say as 184 * well. 185 */ 186 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 187 return spsr; 188 } 189 #else 190 uint32_t hikey960_get_spsr_for_bl33_entry(void) 191 { 192 unsigned int hyp_status, mode, spsr; 193 194 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 195 196 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 197 198 /* 199 * TODO: Consider the possibility of specifying the SPSR in 200 * the FIP ToC and allowing the platform to have a say as 201 * well. 202 */ 203 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 204 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 205 return spsr; 206 } 207 #endif /* __aarch64__ */ 208 209 int hikey960_bl2_handle_post_image_load(unsigned int image_id) 210 { 211 int err = 0; 212 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 213 #ifdef SPD_opteed 214 bl_mem_params_node_t *pager_mem_params = NULL; 215 bl_mem_params_node_t *paged_mem_params = NULL; 216 #endif 217 assert(bl_mem_params); 218 219 switch (image_id) { 220 #ifdef __aarch64__ 221 case BL32_IMAGE_ID: 222 #ifdef SPD_opteed 223 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 224 assert(pager_mem_params); 225 226 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 227 assert(paged_mem_params); 228 229 err = parse_optee_header(&bl_mem_params->ep_info, 230 &pager_mem_params->image_info, 231 &paged_mem_params->image_info); 232 if (err != 0) { 233 WARN("OPTEE header parse error.\n"); 234 } 235 #endif 236 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry(); 237 break; 238 #endif 239 240 case BL33_IMAGE_ID: 241 /* BL33 expects to receive the primary CPU MPID (through r0) */ 242 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 243 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry(); 244 break; 245 246 #ifdef SCP_BL2_BASE 247 case SCP_BL2_IMAGE_ID: 248 /* The subsequent handling of SCP_BL2 is platform specific */ 249 err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info); 250 if (err) { 251 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 252 } 253 break; 254 #endif 255 default: 256 /* Do nothing in default case */ 257 break; 258 } 259 260 return err; 261 } 262 263 /******************************************************************************* 264 * This function can be used by the platforms to update/use image 265 * information for given `image_id`. 266 ******************************************************************************/ 267 int bl2_plat_handle_pre_image_load(unsigned int image_id) 268 { 269 return hikey960_set_fip_addr(image_id, "fip"); 270 } 271 272 int bl2_plat_handle_post_image_load(unsigned int image_id) 273 { 274 return hikey960_bl2_handle_post_image_load(image_id); 275 } 276 277 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 278 u_register_t arg3, u_register_t arg4) 279 { 280 unsigned int id, uart_base; 281 282 generic_delay_timer_init(); 283 hikey960_read_boardid(&id); 284 if (id == 5300) 285 uart_base = PL011_UART5_BASE; 286 else 287 uart_base = PL011_UART6_BASE; 288 /* Initialize the console to provide early debug support */ 289 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 290 PL011_BAUDRATE, &console); 291 /* 292 * Allow BL2 to see the whole Trusted RAM. 293 */ 294 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 295 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 296 } 297 298 void bl2_el3_plat_arch_setup(void) 299 { 300 hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base, 301 bl2_el3_tzram_layout.total_size, 302 BL_CODE_BASE, 303 BL_CODE_END, 304 BL_COHERENT_RAM_BASE, 305 BL_COHERENT_RAM_END); 306 } 307 308 void bl2_platform_setup(void) 309 { 310 /* disable WDT0 */ 311 if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { 312 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); 313 mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0); 314 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0); 315 } 316 hikey960_clk_init(); 317 hikey960_pmu_init(); 318 hikey960_regulator_enable(); 319 hikey960_tzc_init(); 320 hikey960_peri_init(); 321 hikey960_pinmux_init(); 322 hikey960_gpio_init(); 323 hikey960_init_ufs(); 324 hikey960_io_setup(); 325 } 326