1 /* 2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/dw_ufs.h> 20 #include <drivers/generic_delay_timer.h> 21 #include <drivers/partition/partition.h> 22 #include <drivers/ufs.h> 23 #include <lib/mmio.h> 24 #ifdef SPD_opteed 25 #include <lib/optee_utils.h> 26 #endif 27 28 #include <hi3660.h> 29 #include "hikey960_def.h" 30 #include "hikey960_private.h" 31 32 #define BL2_RW_BASE (BL_CODE_END) 33 34 /* BL2 platform parameters passed to BL31 */ 35 static plat_params_from_bl2_t plat_params_from_bl2; 36 37 static meminfo_t bl2_el3_tzram_layout; 38 static console_t console; 39 extern int load_lpm3(void); 40 41 enum { 42 BOOT_MODE_RECOVERY = 0, 43 BOOT_MODE_NORMAL, 44 BOOT_MODE_MASK = 1, 45 }; 46 47 /******************************************************************************* 48 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 49 * Return 0 on success, -1 otherwise. 50 ******************************************************************************/ 51 int plat_hikey960_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 52 { 53 int i; 54 int *buf; 55 56 assert(scp_bl2_image_info->image_size < SCP_BL2_SIZE); 57 58 INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); 59 60 INFO("BL2: SCP_BL2: 0x%lx@0x%x\n", 61 scp_bl2_image_info->image_base, 62 scp_bl2_image_info->image_size); 63 64 buf = (int *)scp_bl2_image_info->image_base; 65 66 INFO("BL2: SCP_BL2 HEAD:\n"); 67 for (i = 0; i < 64; i += 4) 68 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 69 buf[i], buf[i+1], buf[i+2], buf[i+3]); 70 71 buf = (int *)(scp_bl2_image_info->image_base + 72 scp_bl2_image_info->image_size - 256); 73 74 INFO("BL2: SCP_BL2 TAIL:\n"); 75 for (i = 0; i < 64; i += 4) 76 INFO("BL2: SCP_BL2 0x%x 0x%x 0x%x 0x%x\n", 77 buf[i], buf[i+1], buf[i+2], buf[i+3]); 78 79 INFO("BL2: SCP_BL2 transferred to SCP\n"); 80 81 load_lpm3(); 82 (void)buf; 83 84 return 0; 85 } 86 87 static void hikey960_ufs_reset(void) 88 { 89 unsigned int data, mask; 90 91 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 92 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 93 do { 94 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 95 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 96 /* use abb clk */ 97 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 98 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 99 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 100 mdelay(1); 101 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 102 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 103 104 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 105 do { 106 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 107 } while ((data & PERI_UFS_BIT) == 0); 108 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 109 mdelay(1); 110 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 111 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 112 MASK_UFS_DEVICE_RESET); 113 /* clear SC_DIV_UFS_PERIBUS */ 114 mask = SC_DIV_UFS_PERIBUS << 16; 115 mmio_write_32(CRG_CLKDIV17_REG, mask); 116 /* set SC_DIV_UFSPHY_CFG(3) */ 117 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 118 data = SC_DIV_UFSPHY_CFG(3); 119 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 120 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 121 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 122 data |= 0x39; 123 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 124 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 125 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 126 MASK_UFS_CLK_GATE_BYPASS); 127 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 128 129 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 130 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 131 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 132 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 133 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 134 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 135 mdelay(1); 136 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 137 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 138 mdelay(20); 139 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 140 0x03300330); 141 142 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 143 do { 144 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 145 } while (data & PERI_UFS_BIT); 146 } 147 148 static void hikey960_init_ufs(void) 149 { 150 dw_ufs_params_t ufs_params; 151 152 memset(&ufs_params, 0, sizeof(ufs_params_t)); 153 ufs_params.reg_base = UFS_REG_BASE; 154 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 155 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 156 hikey960_ufs_reset(); 157 dw_ufs_init(&ufs_params); 158 } 159 160 /******************************************************************************* 161 * Gets SPSR for BL32 entry 162 ******************************************************************************/ 163 uint32_t hikey960_get_spsr_for_bl32_entry(void) 164 { 165 /* 166 * The Secure Payload Dispatcher service is responsible for 167 * setting the SPSR prior to entry into the BL3-2 image. 168 */ 169 return 0; 170 } 171 172 /******************************************************************************* 173 * Gets SPSR for BL33 entry 174 ******************************************************************************/ 175 #ifdef __aarch64__ 176 uint32_t hikey960_get_spsr_for_bl33_entry(void) 177 { 178 unsigned int mode; 179 uint32_t spsr; 180 181 /* Figure out what mode we enter the non-secure world in */ 182 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 183 184 /* 185 * TODO: Consider the possibility of specifying the SPSR in 186 * the FIP ToC and allowing the platform to have a say as 187 * well. 188 */ 189 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 190 return spsr; 191 } 192 #else 193 uint32_t hikey960_get_spsr_for_bl33_entry(void) 194 { 195 unsigned int hyp_status, mode, spsr; 196 197 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 198 199 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 200 201 /* 202 * TODO: Consider the possibility of specifying the SPSR in 203 * the FIP ToC and allowing the platform to have a say as 204 * well. 205 */ 206 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 207 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 208 return spsr; 209 } 210 #endif /* __aarch64__ */ 211 212 int hikey960_bl2_handle_post_image_load(unsigned int image_id) 213 { 214 int err = 0; 215 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 216 #ifdef SPD_opteed 217 bl_mem_params_node_t *pager_mem_params = NULL; 218 bl_mem_params_node_t *paged_mem_params = NULL; 219 #endif 220 assert(bl_mem_params); 221 222 switch (image_id) { 223 case BL31_IMAGE_ID: 224 /* Pass BL2 platform parameter to BL31 */ 225 bl_mem_params->ep_info.args.arg1 = (uint64_t) &plat_params_from_bl2; 226 break; 227 228 #ifdef __aarch64__ 229 case BL32_IMAGE_ID: 230 #ifdef SPD_opteed 231 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 232 assert(pager_mem_params); 233 234 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 235 assert(paged_mem_params); 236 237 err = parse_optee_header(&bl_mem_params->ep_info, 238 &pager_mem_params->image_info, 239 &paged_mem_params->image_info); 240 if (err != 0) { 241 WARN("OPTEE header parse error.\n"); 242 } 243 #endif 244 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl32_entry(); 245 break; 246 #endif 247 248 case BL33_IMAGE_ID: 249 /* BL33 expects to receive the primary CPU MPID (through r0) */ 250 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 251 bl_mem_params->ep_info.spsr = hikey960_get_spsr_for_bl33_entry(); 252 break; 253 254 #ifdef SCP_BL2_BASE 255 case SCP_BL2_IMAGE_ID: 256 /* The subsequent handling of SCP_BL2 is platform specific */ 257 err = plat_hikey960_bl2_handle_scp_bl2(&bl_mem_params->image_info); 258 if (err) { 259 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 260 } 261 break; 262 #endif 263 default: 264 /* Do nothing in default case */ 265 break; 266 } 267 268 return err; 269 } 270 271 /******************************************************************************* 272 * This function can be used by the platforms to update/use image 273 * information for given `image_id`. 274 ******************************************************************************/ 275 int bl2_plat_handle_pre_image_load(unsigned int image_id) 276 { 277 return hikey960_set_fip_addr(image_id, "fip"); 278 } 279 280 int bl2_plat_handle_post_image_load(unsigned int image_id) 281 { 282 return hikey960_bl2_handle_post_image_load(image_id); 283 } 284 285 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 286 u_register_t arg3, u_register_t arg4) 287 { 288 unsigned int id, uart_base; 289 290 generic_delay_timer_init(); 291 hikey960_read_boardid(&id); 292 if (id == 5300) 293 uart_base = PL011_UART5_BASE; 294 else 295 uart_base = PL011_UART6_BASE; 296 /* Initialize the console to provide early debug support */ 297 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 298 PL011_BAUDRATE, &console); 299 /* 300 * Allow BL2 to see the whole Trusted RAM. 301 */ 302 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 303 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 304 } 305 306 void bl2_el3_plat_arch_setup(void) 307 { 308 hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base, 309 bl2_el3_tzram_layout.total_size, 310 BL_CODE_BASE, 311 BL_CODE_END, 312 BL_COHERENT_RAM_BASE, 313 BL_COHERENT_RAM_END); 314 } 315 316 void bl2_platform_setup(void) 317 { 318 int ret; 319 320 /* disable WDT0 */ 321 if (mmio_read_32(WDT0_REG_BASE + WDT_LOCK_OFFSET) == WDT_LOCKED) { 322 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, WDT_UNLOCK); 323 mmio_write_32(WDT0_REG_BASE + WDT_CONTROL_OFFSET, 0); 324 mmio_write_32(WDT0_REG_BASE + WDT_LOCK_OFFSET, 0); 325 } 326 hikey960_clk_init(); 327 hikey960_pmu_init(); 328 hikey960_regulator_enable(); 329 hikey960_tzc_init(); 330 hikey960_peri_init(); 331 hikey960_pinmux_init(); 332 hikey960_gpio_init(); 333 hikey960_init_ufs(); 334 hikey960_io_setup(); 335 336 /* Read serial number from storage */ 337 plat_params_from_bl2.fastboot_serno = 0; 338 ret = hikey960_load_serialno(&plat_params_from_bl2.fastboot_serno); 339 if (ret != 0) { 340 ERROR("BL2: could not read serial number\n"); 341 } 342 INFO("BL2: fastboot_serno %lx\n", plat_params_from_bl2.fastboot_serno); 343 flush_dcache_range((uintptr_t)&plat_params_from_bl2, sizeof(plat_params_from_bl2_t)); 344 } 345