1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/tbbr/tbbr_img_desc.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/interrupt_props.h> 18 #include <drivers/arm/gicv2.h> 19 #include <drivers/arm/pl011.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/dw_ufs.h> 22 #include <drivers/generic_delay_timer.h> 23 #include <drivers/ufs.h> 24 #include <lib/mmio.h> 25 #include <plat/common/platform.h> 26 27 #include <hi3660.h> 28 #include "hikey960_def.h" 29 #include "hikey960_private.h" 30 31 enum { 32 BOOT_MODE_RECOVERY = 0, 33 BOOT_MODE_NORMAL, 34 BOOT_MODE_MASK = 1, 35 }; 36 37 /* 38 * Declarations of linker defined symbols which will help us find the layout 39 * of trusted RAM 40 */ 41 42 /* Data structure which holds the extents of the trusted RAM for BL1 */ 43 static meminfo_t bl1_tzram_layout; 44 static console_pl011_t console; 45 46 /****************************************************************************** 47 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 48 * interrupts. 49 *****************************************************************************/ 50 static const interrupt_prop_t g0_interrupt_props[] = { 51 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 52 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 53 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 54 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 55 }; 56 57 const gicv2_driver_data_t hikey960_gic_data = { 58 .gicd_base = GICD_REG_BASE, 59 .gicc_base = GICC_REG_BASE, 60 .interrupt_props = g0_interrupt_props, 61 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 62 }; 63 64 meminfo_t *bl1_plat_sec_mem_layout(void) 65 { 66 return &bl1_tzram_layout; 67 } 68 69 /* 70 * Perform any BL1 specific platform actions. 71 */ 72 void bl1_early_platform_setup(void) 73 { 74 unsigned int id, uart_base; 75 76 generic_delay_timer_init(); 77 hikey960_read_boardid(&id); 78 if (id == 5300) 79 uart_base = PL011_UART5_BASE; 80 else 81 uart_base = PL011_UART6_BASE; 82 /* Initialize the console to provide early debug support */ 83 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 84 PL011_BAUDRATE, &console); 85 86 /* Allow BL1 to see the whole Trusted RAM */ 87 bl1_tzram_layout.total_base = BL1_RW_BASE; 88 bl1_tzram_layout.total_size = BL1_RW_SIZE; 89 90 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 91 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 92 } 93 94 /* 95 * Perform the very early platform specific architecture setup here. At the 96 * moment this only does basic initialization. Later architectural setup 97 * (bl1_arch_setup()) does not do anything platform specific. 98 */ 99 void bl1_plat_arch_setup(void) 100 { 101 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 102 bl1_tzram_layout.total_size, 103 BL1_RO_BASE, 104 BL1_RO_LIMIT, 105 BL_COHERENT_RAM_BASE, 106 BL_COHERENT_RAM_END); 107 } 108 109 static void hikey960_ufs_reset(void) 110 { 111 unsigned int data, mask; 112 113 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 115 do { 116 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 117 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 118 /* use abb clk */ 119 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 120 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 121 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 122 mdelay(1); 123 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 125 126 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 127 do { 128 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 129 } while ((data & PERI_UFS_BIT) == 0); 130 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 131 mdelay(1); 132 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 133 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 134 MASK_UFS_DEVICE_RESET); 135 /* clear SC_DIV_UFS_PERIBUS */ 136 mask = SC_DIV_UFS_PERIBUS << 16; 137 mmio_write_32(CRG_CLKDIV17_REG, mask); 138 /* set SC_DIV_UFSPHY_CFG(3) */ 139 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 140 data = SC_DIV_UFSPHY_CFG(3); 141 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 142 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 143 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 144 data |= 0x39; 145 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 147 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 148 MASK_UFS_CLK_GATE_BYPASS); 149 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 150 151 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 152 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 153 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 154 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 155 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 156 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 157 mdelay(1); 158 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 159 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 160 mdelay(20); 161 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 162 0x03300330); 163 164 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 165 do { 166 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 167 } while (data & PERI_UFS_BIT); 168 } 169 170 static void hikey960_ufs_init(void) 171 { 172 dw_ufs_params_t ufs_params; 173 174 memset(&ufs_params, 0, sizeof(ufs_params)); 175 ufs_params.reg_base = UFS_REG_BASE; 176 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 177 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 178 179 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 180 hikey960_ufs_reset(); 181 dw_ufs_init(&ufs_params); 182 } 183 184 /* 185 * Function which will perform any remaining platform-specific setup that can 186 * occur after the MMU and data cache have been enabled. 187 */ 188 void bl1_platform_setup(void) 189 { 190 hikey960_clk_init(); 191 hikey960_pmu_init(); 192 hikey960_regulator_enable(); 193 hikey960_tzc_init(); 194 hikey960_peri_init(); 195 hikey960_ufs_init(); 196 hikey960_pinmux_init(); 197 hikey960_gpio_init(); 198 hikey960_io_setup(); 199 } 200 201 /* 202 * The following function checks if Firmware update is needed, 203 * by checking if TOC in FIP image is valid or not. 204 */ 205 unsigned int bl1_plat_get_next_image_id(void) 206 { 207 unsigned int mode, ret; 208 209 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 210 switch (mode & BOOT_MODE_MASK) { 211 case BOOT_MODE_RECOVERY: 212 ret = NS_BL1U_IMAGE_ID; 213 break; 214 default: 215 WARN("Invalid boot mode is found:%d\n", mode); 216 panic(); 217 } 218 return ret; 219 } 220 221 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 222 { 223 unsigned int index = 0; 224 225 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 226 if (bl1_tbbr_image_descs[index].image_id == image_id) 227 return &bl1_tbbr_image_descs[index]; 228 index++; 229 } 230 231 return NULL; 232 } 233 234 void bl1_plat_set_ep_info(unsigned int image_id, 235 entry_point_info_t *ep_info) 236 { 237 unsigned int data = 0; 238 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 239 240 if (image_id != NS_BL1U_IMAGE_ID) 241 panic(); 242 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 243 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 244 NS_BL1U_SIZE); 245 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 246 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 247 /* Initialize the GIC driver, cpu and distributor interfaces */ 248 gicv2_driver_init(&hikey960_gic_data); 249 gicv2_distif_init(); 250 gicv2_pcpu_distif_init(); 251 gicv2_cpuif_enable(); 252 /* CNTFRQ is read-only in EL1 */ 253 write_cntfrq_el0(plat_get_syscnt_freq2()); 254 data = read_cpacr_el1(); 255 do { 256 data |= 3 << 20; 257 write_cpacr_el1(data); 258 data = read_cpacr_el1(); 259 } while ((data & (3 << 20)) != (3 << 20)); 260 INFO("cpacr_el1:0x%x\n", data); 261 262 ep_info->args.arg0 = 0xffff & read_mpidr(); 263 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 264 DISABLE_ALL_EXCEPTIONS); 265 } 266