1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_gic.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <dw_ufs.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <gicv2.h> 18 #include <hi3660.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 extern unsigned long __COHERENT_RAM_START__; 41 extern unsigned long __COHERENT_RAM_END__; 42 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 51 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 52 53 /* Data structure which holds the extents of the trusted RAM for BL1 */ 54 static meminfo_t bl1_tzram_layout; 55 56 /****************************************************************************** 57 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 58 * interrupts. 59 *****************************************************************************/ 60 const unsigned int g0_interrupt_array[] = { 61 IRQ_SEC_PHY_TIMER, 62 IRQ_SEC_SGI_0 63 }; 64 65 const gicv2_driver_data_t hikey960_gic_data = { 66 .gicd_base = GICD_REG_BASE, 67 .gicc_base = GICC_REG_BASE, 68 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 69 .g0_interrupt_array = g0_interrupt_array, 70 }; 71 72 meminfo_t *bl1_plat_sec_mem_layout(void) 73 { 74 return &bl1_tzram_layout; 75 } 76 77 #if LOAD_IMAGE_V2 78 /******************************************************************************* 79 * Function that takes a memory layout into which BL2 has been loaded and 80 * populates a new memory layout for BL2 that ensures that BL1's data sections 81 * resident in secure RAM are not visible to BL2. 82 ******************************************************************************/ 83 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 84 meminfo_t *bl2_mem_layout) 85 { 86 87 assert(bl1_mem_layout != NULL); 88 assert(bl2_mem_layout != NULL); 89 90 /* 91 * Cannot remove BL1 RW data from the scope of memory visible to BL2 92 * like arm platforms because they overlap in hikey960 93 */ 94 bl2_mem_layout->total_base = BL2_BASE; 95 bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE; 96 97 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 98 } 99 #endif /* LOAD_IMAGE_V2 */ 100 101 /* 102 * Perform any BL1 specific platform actions. 103 */ 104 void bl1_early_platform_setup(void) 105 { 106 unsigned int id, uart_base; 107 108 generic_delay_timer_init(); 109 hikey960_read_boardid(&id); 110 if (id == 5300) 111 uart_base = PL011_UART5_BASE; 112 else 113 uart_base = PL011_UART6_BASE; 114 /* Initialize the console to provide early debug support */ 115 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 116 117 /* Allow BL1 to see the whole Trusted RAM */ 118 bl1_tzram_layout.total_base = BL1_RW_BASE; 119 bl1_tzram_layout.total_size = BL1_RW_SIZE; 120 121 #if !LOAD_IMAGE_V2 122 /* Calculate how much RAM BL1 is using and how much remains free */ 123 bl1_tzram_layout.free_base = BL1_RW_BASE; 124 bl1_tzram_layout.free_size = BL1_RW_SIZE; 125 reserve_mem(&bl1_tzram_layout.free_base, 126 &bl1_tzram_layout.free_size, 127 BL1_RAM_BASE, 128 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 129 #endif /* LOAD_IMAGE_V2 */ 130 131 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 132 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 133 } 134 135 /* 136 * Perform the very early platform specific architecture setup here. At the 137 * moment this only does basic initialization. Later architectural setup 138 * (bl1_arch_setup()) does not do anything platform specific. 139 */ 140 void bl1_plat_arch_setup(void) 141 { 142 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 143 bl1_tzram_layout.total_size, 144 BL1_RO_BASE, 145 BL1_RO_LIMIT, 146 BL1_COHERENT_RAM_BASE, 147 BL1_COHERENT_RAM_LIMIT); 148 } 149 150 static void hikey960_clk_init(void) 151 { 152 /* change ldi0 sel to ppll2 */ 153 mmio_write_32(0xfff350b4, 0xf0002000); 154 /* ldi0 20' */ 155 mmio_write_32(0xfff350bc, 0xfc004c00); 156 } 157 158 static void hikey960_pmu_init(void) 159 { 160 /* clear np_xo_abb_dig_START bit in PMIC_CLK_TOP_CTRL7 register */ 161 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); 162 } 163 164 static void hikey960_enable_ppll3(void) 165 { 166 /* enable ppll3 */ 167 mmio_write_32(PMC_PPLL3_CTRL0_REG, 0x4904305); 168 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x2300000); 169 mmio_write_32(PMC_PPLL3_CTRL1_REG, 0x6300000); 170 } 171 172 static void bus_idle_clear(unsigned int value) 173 { 174 unsigned int pmc_value, value1, value2; 175 int timeout = 100; 176 177 pmc_value = value << 16; 178 pmc_value &= ~value; 179 mmio_write_32(PMC_NOC_POWER_IDLEREQ_REG, pmc_value); 180 181 for (;;) { 182 value1 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLEACK_REG); 183 value2 = (unsigned int)mmio_read_32(PMC_NOC_POWER_IDLE_REG); 184 if (((value1 & value) == 0) && ((value2 & value) == 0)) 185 break; 186 udelay(1); 187 timeout--; 188 if (timeout <= 0) { 189 WARN("%s timeout\n", __func__); 190 break; 191 } 192 } 193 } 194 195 static void set_vivobus_power_up(void) 196 { 197 /* clk enable */ 198 mmio_write_32(CRG_CLKDIV20_REG, 0x00020002); 199 mmio_write_32(CRG_PEREN0_REG, 0x00001000); 200 } 201 202 static void set_dss_power_up(void) 203 { 204 /* set edc0 133MHz = 1600MHz / 12 */ 205 mmio_write_32(CRG_CLKDIV5_REG, 0x003f000b); 206 /* set ldi0 ppl0 */ 207 mmio_write_32(CRG_CLKDIV3_REG, 0xf0001000); 208 /* set ldi0 133MHz, 1600MHz / 12 */ 209 mmio_write_32(CRG_CLKDIV5_REG, 0xfc002c00); 210 /* mtcmos on */ 211 mmio_write_32(CRG_PERPWREN_REG, 0x00000020); 212 udelay(100); 213 /* DISP CRG */ 214 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000010); 215 /* clk enable */ 216 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 217 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 218 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 219 udelay(1); 220 /* clk disable */ 221 mmio_write_32(CRG_PERDIS3_REG, 0x0003b000); 222 mmio_write_32(CRG_PERDIS0_REG, 0x00002000); 223 mmio_write_32(CRG_CLKDIV18_REG, 0x01400000); 224 udelay(1); 225 /* iso disable */ 226 mmio_write_32(CRG_ISODIS_REG, 0x00000040); 227 /* unreset */ 228 mmio_write_32(CRG_PERRSTDIS4_REG, 0x00000006); 229 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000c00); 230 /* clk enable */ 231 mmio_write_32(CRG_CLKDIV18_REG, 0x01400140); 232 mmio_write_32(CRG_PEREN0_REG, 0x00002000); 233 mmio_write_32(CRG_PEREN3_REG, 0x0003b000); 234 /* bus idle clear */ 235 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_DSS); 236 /* set edc0 400MHz for 2K 1600MHz / 4 */ 237 mmio_write_32(CRG_CLKDIV5_REG, 0x003f0003); 238 /* set ldi 266MHz, 1600MHz / 6 */ 239 mmio_write_32(CRG_CLKDIV5_REG, 0xfc001400); 240 } 241 242 static void set_vcodec_power_up(void) 243 { 244 /* clk enable */ 245 mmio_write_32(CRG_CLKDIV20_REG, 0x00040004); 246 mmio_write_32(CRG_PEREN0_REG, 0x00000060); 247 mmio_write_32(CRG_PEREN2_REG, 0x10000000); 248 /* unreset */ 249 mmio_write_32(CRG_PERRSTDIS0_REG, 0x00000018); 250 /* bus idle clear */ 251 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VCODEC); 252 } 253 254 static void set_vdec_power_up(void) 255 { 256 /* mtcmos on */ 257 mmio_write_32(CRG_PERPWREN_REG, 0x00000004); 258 udelay(100); 259 /* clk enable */ 260 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 261 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 262 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 263 udelay(1); 264 /* clk disable */ 265 mmio_write_32(CRG_PERDIS3_REG, 0x00000800); 266 mmio_write_32(CRG_PERDIS2_REG, 0x20080000); 267 mmio_write_32(CRG_CLKDIV18_REG, 0x80000000); 268 udelay(1); 269 /* iso disable */ 270 mmio_write_32(CRG_ISODIS_REG, 0x00000004); 271 /* unreset */ 272 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000200); 273 /* clk enable */ 274 mmio_write_32(CRG_CLKDIV18_REG, 0x80008000); 275 mmio_write_32(CRG_PEREN2_REG, 0x20080000); 276 mmio_write_32(CRG_PEREN3_REG, 0x00000800); 277 /* bus idle clear */ 278 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VDEC); 279 } 280 281 static void set_venc_power_up(void) 282 { 283 /* set venc ppll3 */ 284 mmio_write_32(CRG_CLKDIV8_REG, 0x18001000); 285 /* set venc 258MHz, 1290MHz / 5 */ 286 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00100); 287 /* mtcmos on */ 288 mmio_write_32(CRG_PERPWREN_REG, 0x00000002); 289 udelay(100); 290 /* clk enable */ 291 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 292 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 293 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 294 udelay(1); 295 /* clk disable */ 296 mmio_write_32(CRG_PERDIS3_REG, 0x00000400); 297 mmio_write_32(CRG_PERDIS2_REG, 0x40000100); 298 mmio_write_32(CRG_CLKDIV19_REG, 0x00010000); 299 udelay(1); 300 /* iso disable */ 301 mmio_write_32(CRG_ISODIS_REG, 0x00000002); 302 /* unreset */ 303 mmio_write_32(CRG_PERRSTDIS3_REG, 0x00000100); 304 /* clk enable */ 305 mmio_write_32(CRG_CLKDIV19_REG, 0x00010001); 306 mmio_write_32(CRG_PEREN2_REG, 0x40000100); 307 mmio_write_32(CRG_PEREN3_REG, 0x00000400); 308 /* bus idle clear */ 309 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_VENC); 310 /* set venc 645MHz, 1290MHz / 2 */ 311 mmio_write_32(CRG_CLKDIV8_REG, 0x07c00040); 312 } 313 314 static void set_isp_power_up(void) 315 { 316 /* mtcmos on */ 317 mmio_write_32(CRG_PERPWREN_REG, 0x00000001); 318 udelay(100); 319 /* clk enable */ 320 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 321 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 322 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 323 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 324 udelay(1); 325 /* clk disable */ 326 mmio_write_32(CRG_PERDIS5_REG, 0x01000010); 327 mmio_write_32(CRG_PERDIS3_REG, 0x0bf00000); 328 mmio_write_32(CRG_CLKDIV18_REG, 0x70000000); 329 mmio_write_32(CRG_CLKDIV20_REG, 0x00100000); 330 udelay(1); 331 /* iso disable */ 332 mmio_write_32(CRG_ISODIS_REG, 0x00000001); 333 /* unreset */ 334 mmio_write_32(CRG_ISP_SEC_RSTDIS_REG, 0x0000002f); 335 /* clk enable */ 336 mmio_write_32(CRG_CLKDIV18_REG, 0x70007000); 337 mmio_write_32(CRG_CLKDIV20_REG, 0x00100010); 338 mmio_write_32(CRG_PEREN5_REG, 0x01000010); 339 mmio_write_32(CRG_PEREN3_REG, 0x0bf00000); 340 /* bus idle clear */ 341 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_ISP); 342 /* csi clk enable */ 343 mmio_write_32(CRG_PEREN3_REG, 0x00700000); 344 } 345 346 static void set_ivp_power_up(void) 347 { 348 /* set ivp ppll0 */ 349 mmio_write_32(CRG_CLKDIV0_REG, 0xc0000000); 350 /* set ivp 267MHz, 1600MHz / 6 */ 351 mmio_write_32(CRG_CLKDIV0_REG, 0x3c001400); 352 /* mtcmos on */ 353 mmio_write_32(CRG_PERPWREN_REG, 0x00200000); 354 udelay(100); 355 /* IVP CRG unreset */ 356 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000001); 357 /* clk enable */ 358 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 359 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 360 udelay(1); 361 /* clk disable */ 362 mmio_write_32(CRG_PERDIS4_REG, 0x000000a8); 363 mmio_write_32(CRG_CLKDIV20_REG, 0x02000000); 364 udelay(1); 365 /* iso disable */ 366 mmio_write_32(CRG_ISODIS_REG, 0x01000000); 367 /* unreset */ 368 mmio_write_32(CRG_IVP_SEC_RSTDIS_REG, 0x00000002); 369 /* clk enable */ 370 mmio_write_32(CRG_CLKDIV20_REG, 0x02000200); 371 mmio_write_32(CRG_PEREN4_REG, 0x000000a8); 372 /* bus idle clear */ 373 bus_idle_clear(PMC_NOC_POWER_IDLEREQ_IVP); 374 /* set ivp 533MHz, 1600MHz / 3 */ 375 mmio_write_32(CRG_CLKDIV0_REG, 0x3c000800); 376 } 377 378 static void set_audio_power_up(void) 379 { 380 unsigned int ret; 381 int timeout = 100; 382 /* mtcmos on */ 383 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000001); 384 udelay(100); 385 /* clk enable */ 386 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 387 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 388 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 389 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 390 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 391 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 392 udelay(1); 393 /* clk disable */ 394 mmio_write_32(SCTRL_SCPERDIS1_REG, 0x0000000f); 395 mmio_write_32(SCTRL_SCPERDIS0_REG, 0x0c000000); 396 mmio_write_32(CRG_PERDIS5_REG, 0x00000080); 397 mmio_write_32(CRG_PERDIS0_REG, 0x04000000); 398 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010000); 399 mmio_write_32(CRG_CLKDIV19_REG, 0x80100000); 400 udelay(1); 401 /* iso disable */ 402 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000001); 403 udelay(1); 404 /* unreset */ 405 mmio_write_32(SCTRL_PERRSTDIS1_SEC_REG, 0x00000001); 406 mmio_write_32(SCTRL_SCPERRSTDIS0_REG, 0x00000780); 407 /* clk enable */ 408 mmio_write_32(CRG_CLKDIV19_REG, 0x80108010); 409 mmio_write_32(SCTRL_SCCLKDIV2_REG, 0x00010001); 410 mmio_write_32(SCTRL_SCPEREN0_REG, 0x0c000000); 411 mmio_write_32(CRG_PEREN0_REG, 0x04000000); 412 mmio_write_32(CRG_PEREN5_REG, 0x00000080); 413 mmio_write_32(SCTRL_SCPEREN1_REG, 0x0000000f); 414 /* bus idle clear */ 415 mmio_write_32(SCTRL_SCPERCTRL7_REG, 0x00040000); 416 for (;;) { 417 ret = mmio_read_32(SCTRL_SCPERSTAT6_REG); 418 if (((ret & (1 << 5)) == 0) && ((ret & (1 << 8)) == 0)) 419 break; 420 udelay(1); 421 timeout--; 422 if (timeout <= 0) { 423 WARN("%s timeout\n", __func__); 424 break; 425 } 426 } 427 mmio_write_32(ASP_CFG_MMBUF_CTRL_REG, 0x00ff0000); 428 } 429 430 static void set_pcie_power_up(void) 431 { 432 /* mtcmos on */ 433 mmio_write_32(SCTRL_SCPWREN_REG, 0x00000010); 434 udelay(100); 435 /* clk enable */ 436 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 437 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 438 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 439 udelay(1); 440 /* clk disable */ 441 mmio_write_32(SCTRL_SCPERDIS2_REG, 0x00104000); 442 mmio_write_32(CRG_PERDIS7_REG, 0x000003a0); 443 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000000); 444 udelay(1); 445 /* iso disable */ 446 mmio_write_32(SCTRL_SCISODIS_REG, 0x00000030); 447 /* unreset */ 448 mmio_write_32(CRG_PERRSTDIS3_REG, 0x8c000000); 449 /* clk enable */ 450 mmio_write_32(SCTRL_SCCLKDIV6_REG, 0x08000800); 451 mmio_write_32(SCTRL_SCPEREN2_REG, 0x00104000); 452 mmio_write_32(CRG_PEREN7_REG, 0x000003a0); 453 } 454 455 static void ispfunc_enable(void) 456 { 457 /* enable ispfunc. Otherwise powerup isp_srt causes exception. */ 458 mmio_write_32(0xfff35000, 0x00000008); 459 mmio_write_32(0xfff35460, 0xc004ffff); 460 mmio_write_32(0xfff35030, 0x02000000); 461 mdelay(10); 462 } 463 464 static void isps_control_clock(int flag) 465 { 466 unsigned int ret; 467 468 /* flag: 0 -- disable clock, 1 -- enable clock */ 469 if (flag) { 470 ret = mmio_read_32(0xe8420364); 471 ret |= 1; 472 mmio_write_32(0xe8420364, ret); 473 } else { 474 ret = mmio_read_32(0xe8420364); 475 ret &= ~1; 476 mmio_write_32(0xe8420364, ret); 477 } 478 } 479 480 static void set_isp_srt_power_up(void) 481 { 482 unsigned int ret; 483 484 ispfunc_enable(); 485 /* reset */ 486 mmio_write_32(0xe8420374, 0x00000001); 487 mmio_write_32(0xe8420350, 0x00000000); 488 mmio_write_32(0xe8420358, 0x00000000); 489 /* mtcmos on */ 490 mmio_write_32(0xfff35150, 0x00400000); 491 udelay(100); 492 /* clk enable */ 493 isps_control_clock(1); 494 udelay(1); 495 isps_control_clock(0); 496 udelay(1); 497 /* iso disable */ 498 mmio_write_32(0xfff35148, 0x08000000); 499 /* unreset */ 500 ret = mmio_read_32(0xe8420374); 501 ret &= ~0x1; 502 mmio_write_32(0xe8420374, ret); 503 /* clk enable */ 504 isps_control_clock(1); 505 /* enable clock gating for accessing csi registers */ 506 mmio_write_32(0xe8420010, ~0); 507 } 508 509 static void hikey960_regulator_enable(void) 510 { 511 set_vivobus_power_up(); 512 hikey960_enable_ppll3(); 513 set_dss_power_up(); 514 set_vcodec_power_up(); 515 set_vdec_power_up(); 516 set_venc_power_up(); 517 set_isp_power_up(); 518 set_ivp_power_up(); 519 set_audio_power_up(); 520 set_pcie_power_up(); 521 set_isp_srt_power_up(); 522 523 /* set ISP_CORE_CTRL_S to unsecure mode */ 524 mmio_write_32(0xe8583800, 0x7); 525 /* set ISP_SUB_CTRL_S to unsecure mode */ 526 mmio_write_32(0xe8583804, 0xf); 527 } 528 529 static void hikey960_ufs_reset(void) 530 { 531 unsigned int data, mask; 532 533 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 534 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 535 do { 536 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 537 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 538 /* use abb clk */ 539 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 540 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 541 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 542 mdelay(1); 543 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 544 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 545 546 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 547 do { 548 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 549 } while ((data & PERI_UFS_BIT) == 0); 550 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 551 mdelay(1); 552 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 553 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 554 MASK_UFS_DEVICE_RESET); 555 /* clear SC_DIV_UFS_PERIBUS */ 556 mask = SC_DIV_UFS_PERIBUS << 16; 557 mmio_write_32(CRG_CLKDIV17_REG, mask); 558 /* set SC_DIV_UFSPHY_CFG(3) */ 559 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 560 data = SC_DIV_UFSPHY_CFG(3); 561 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 562 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 563 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 564 data |= 0x39; 565 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 566 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 567 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 568 MASK_UFS_CLK_GATE_BYPASS); 569 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 570 571 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 572 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 573 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 574 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 575 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 576 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 577 mdelay(1); 578 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 579 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 580 mdelay(20); 581 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 582 0x03300330); 583 584 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 585 do { 586 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 587 } while (data & PERI_UFS_BIT); 588 } 589 590 static void hikey960_ufs_init(void) 591 { 592 dw_ufs_params_t ufs_params; 593 594 memset(&ufs_params, 0, sizeof(ufs_params)); 595 ufs_params.reg_base = UFS_REG_BASE; 596 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 597 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 598 599 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 600 hikey960_ufs_reset(); 601 dw_ufs_init(&ufs_params); 602 } 603 604 static void hikey960_tzc_init(void) 605 { 606 mmio_write_32(TZC_EN0_REG, 0x7fbff066); 607 mmio_write_32(TZC_EN1_REG, 0xfffff5fc); 608 mmio_write_32(TZC_EN2_REG, 0x0007005c); 609 mmio_write_32(TZC_EN3_REG, 0x37030700); 610 mmio_write_32(TZC_EN4_REG, 0xf63fefae); 611 mmio_write_32(TZC_EN5_REG, 0x000410fd); 612 mmio_write_32(TZC_EN6_REG, 0x0063ff68); 613 mmio_write_32(TZC_EN7_REG, 0x030000f3); 614 mmio_write_32(TZC_EN8_REG, 0x00000007); 615 } 616 617 static void hikey960_peri_init(void) 618 { 619 /* unreset */ 620 mmio_setbits_32(CRG_PERRSTDIS4_REG, 1); 621 } 622 623 static void hikey960_pinmux_init(void) 624 { 625 unsigned int id; 626 627 hikey960_read_boardid(&id); 628 if (id == 5301) { 629 /* hikey960 hardware v2 */ 630 /* GPIO150: LED */ 631 mmio_write_32(IOMG_FIX_006_REG, 0); 632 /* GPIO151: LED */ 633 mmio_write_32(IOMG_FIX_007_REG, 0); 634 /* GPIO189: LED */ 635 mmio_write_32(IOMG_AO_011_REG, 0); 636 /* GPIO190: LED */ 637 mmio_write_32(IOMG_AO_012_REG, 0); 638 /* GPIO46 */ 639 mmio_write_32(IOMG_044_REG, 0); 640 /* GPIO202 */ 641 mmio_write_32(IOMG_AO_023_REG, 0); 642 /* GPIO206 */ 643 mmio_write_32(IOMG_AO_026_REG, 0); 644 /* GPIO219 - PD pullup */ 645 mmio_write_32(IOMG_AO_039_REG, 0); 646 mmio_write_32(IOCG_AO_043_REG, 1 << 0); 647 } 648 /* GPIO005 - PMU SSI, 10mA */ 649 mmio_write_32(IOCG_006_REG, 2 << 4); 650 /* GPIO213 - PCIE_CLKREQ_N */ 651 mmio_write_32(IOMG_AO_033_REG, 1); 652 } 653 654 /* 655 * Function which will perform any remaining platform-specific setup that can 656 * occur after the MMU and data cache have been enabled. 657 */ 658 void bl1_platform_setup(void) 659 { 660 hikey960_clk_init(); 661 hikey960_pmu_init(); 662 hikey960_regulator_enable(); 663 hikey960_tzc_init(); 664 hikey960_peri_init(); 665 hikey960_ufs_init(); 666 hikey960_pinmux_init(); 667 hikey960_io_setup(); 668 } 669 670 /* 671 * The following function checks if Firmware update is needed, 672 * by checking if TOC in FIP image is valid or not. 673 */ 674 unsigned int bl1_plat_get_next_image_id(void) 675 { 676 unsigned int mode, ret; 677 678 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 679 switch (mode & BOOT_MODE_MASK) { 680 case BOOT_MODE_RECOVERY: 681 ret = NS_BL1U_IMAGE_ID; 682 break; 683 case BOOT_MODE_NORMAL: 684 ret = BL2_IMAGE_ID; 685 break; 686 default: 687 WARN("Invalid boot mode is found:%d\n", mode); 688 panic(); 689 } 690 return ret; 691 } 692 693 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 694 { 695 unsigned int index = 0; 696 697 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 698 if (bl1_tbbr_image_descs[index].image_id == image_id) 699 return &bl1_tbbr_image_descs[index]; 700 index++; 701 } 702 703 return NULL; 704 } 705 706 void bl1_plat_set_ep_info(unsigned int image_id, 707 entry_point_info_t *ep_info) 708 { 709 unsigned int data = 0; 710 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 711 712 if (image_id == BL2_IMAGE_ID) 713 return; 714 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 715 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 716 NS_BL1U_SIZE); 717 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 718 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 719 /* Initialize the GIC driver, cpu and distributor interfaces */ 720 gicv2_driver_init(&hikey960_gic_data); 721 gicv2_distif_init(); 722 gicv2_pcpu_distif_init(); 723 gicv2_cpuif_enable(); 724 /* CNTFRQ is read-only in EL1 */ 725 write_cntfrq_el0(plat_get_syscnt_freq2()); 726 data = read_cpacr_el1(); 727 do { 728 data |= 3 << 20; 729 write_cpacr_el1(data); 730 data = read_cpacr_el1(); 731 } while ((data & (3 << 20)) != (3 << 20)); 732 INFO("cpacr_el1:0x%x\n", data); 733 734 ep_info->args.arg0 = 0xffff & read_mpidr(); 735 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 736 DISABLE_ALL_EXCEPTIONS); 737 } 738