1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_gic.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <dw_ufs.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <gicv2.h> 18 #include <hi3660.h> 19 #include <mmio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <string.h> 23 #include <tbbr/tbbr_img_desc.h> 24 #include <ufs.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey960_def.h" 28 #include "hikey960_private.h" 29 30 enum { 31 BOOT_MODE_RECOVERY = 0, 32 BOOT_MODE_NORMAL, 33 BOOT_MODE_MASK = 1, 34 }; 35 36 /* 37 * Declarations of linker defined symbols which will help us find the layout 38 * of trusted RAM 39 */ 40 extern unsigned long __COHERENT_RAM_START__; 41 extern unsigned long __COHERENT_RAM_END__; 42 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 51 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 52 53 /* Data structure which holds the extents of the trusted RAM for BL1 */ 54 static meminfo_t bl1_tzram_layout; 55 56 /****************************************************************************** 57 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 58 * interrupts. 59 *****************************************************************************/ 60 const unsigned int g0_interrupt_array[] = { 61 IRQ_SEC_PHY_TIMER, 62 IRQ_SEC_SGI_0 63 }; 64 65 const gicv2_driver_data_t hikey960_gic_data = { 66 .gicd_base = GICD_REG_BASE, 67 .gicc_base = GICC_REG_BASE, 68 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 69 .g0_interrupt_array = g0_interrupt_array, 70 }; 71 72 meminfo_t *bl1_plat_sec_mem_layout(void) 73 { 74 return &bl1_tzram_layout; 75 } 76 77 /******************************************************************************* 78 * Function that takes a memory layout into which BL2 has been loaded and 79 * populates a new memory layout for BL2 that ensures that BL1's data sections 80 * resident in secure RAM are not visible to BL2. 81 ******************************************************************************/ 82 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 83 meminfo_t *bl2_mem_layout) 84 { 85 86 assert(bl1_mem_layout != NULL); 87 assert(bl2_mem_layout != NULL); 88 89 /* 90 * Cannot remove BL1 RW data from the scope of memory visible to BL2 91 * like arm platforms because they overlap in hikey960 92 */ 93 bl2_mem_layout->total_base = BL2_BASE; 94 bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE; 95 96 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 97 } 98 99 /* 100 * Perform any BL1 specific platform actions. 101 */ 102 void bl1_early_platform_setup(void) 103 { 104 unsigned int id, uart_base; 105 106 generic_delay_timer_init(); 107 hikey960_read_boardid(&id); 108 if (id == 5300) 109 uart_base = PL011_UART5_BASE; 110 else 111 uart_base = PL011_UART6_BASE; 112 /* Initialize the console to provide early debug support */ 113 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 114 115 /* Allow BL1 to see the whole Trusted RAM */ 116 bl1_tzram_layout.total_base = BL1_RW_BASE; 117 bl1_tzram_layout.total_size = BL1_RW_SIZE; 118 119 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 120 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 121 } 122 123 /* 124 * Perform the very early platform specific architecture setup here. At the 125 * moment this only does basic initialization. Later architectural setup 126 * (bl1_arch_setup()) does not do anything platform specific. 127 */ 128 void bl1_plat_arch_setup(void) 129 { 130 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 131 bl1_tzram_layout.total_size, 132 BL1_RO_BASE, 133 BL1_RO_LIMIT, 134 BL1_COHERENT_RAM_BASE, 135 BL1_COHERENT_RAM_LIMIT); 136 } 137 138 static void hikey960_ufs_reset(void) 139 { 140 unsigned int data, mask; 141 142 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 143 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 144 do { 145 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 146 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 147 /* use abb clk */ 148 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 149 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 150 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 151 mdelay(1); 152 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 153 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 154 155 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 156 do { 157 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 158 } while ((data & PERI_UFS_BIT) == 0); 159 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 160 mdelay(1); 161 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 162 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 163 MASK_UFS_DEVICE_RESET); 164 /* clear SC_DIV_UFS_PERIBUS */ 165 mask = SC_DIV_UFS_PERIBUS << 16; 166 mmio_write_32(CRG_CLKDIV17_REG, mask); 167 /* set SC_DIV_UFSPHY_CFG(3) */ 168 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 169 data = SC_DIV_UFSPHY_CFG(3); 170 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 171 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 172 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 173 data |= 0x39; 174 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 175 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 176 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 177 MASK_UFS_CLK_GATE_BYPASS); 178 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 179 180 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 181 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 182 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 183 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 184 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 185 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 186 mdelay(1); 187 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 188 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 189 mdelay(20); 190 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 191 0x03300330); 192 193 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 194 do { 195 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 196 } while (data & PERI_UFS_BIT); 197 } 198 199 static void hikey960_ufs_init(void) 200 { 201 dw_ufs_params_t ufs_params; 202 203 memset(&ufs_params, 0, sizeof(ufs_params)); 204 ufs_params.reg_base = UFS_REG_BASE; 205 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 206 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 207 208 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 209 hikey960_ufs_reset(); 210 dw_ufs_init(&ufs_params); 211 } 212 213 /* 214 * Function which will perform any remaining platform-specific setup that can 215 * occur after the MMU and data cache have been enabled. 216 */ 217 void bl1_platform_setup(void) 218 { 219 hikey960_clk_init(); 220 hikey960_pmu_init(); 221 hikey960_regulator_enable(); 222 hikey960_tzc_init(); 223 hikey960_peri_init(); 224 hikey960_ufs_init(); 225 hikey960_pinmux_init(); 226 hikey960_io_setup(); 227 } 228 229 /* 230 * The following function checks if Firmware update is needed, 231 * by checking if TOC in FIP image is valid or not. 232 */ 233 unsigned int bl1_plat_get_next_image_id(void) 234 { 235 unsigned int mode, ret; 236 237 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 238 switch (mode & BOOT_MODE_MASK) { 239 case BOOT_MODE_RECOVERY: 240 ret = NS_BL1U_IMAGE_ID; 241 break; 242 default: 243 WARN("Invalid boot mode is found:%d\n", mode); 244 panic(); 245 } 246 return ret; 247 } 248 249 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 250 { 251 unsigned int index = 0; 252 253 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 254 if (bl1_tbbr_image_descs[index].image_id == image_id) 255 return &bl1_tbbr_image_descs[index]; 256 index++; 257 } 258 259 return NULL; 260 } 261 262 void bl1_plat_set_ep_info(unsigned int image_id, 263 entry_point_info_t *ep_info) 264 { 265 unsigned int data = 0; 266 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 267 268 if (image_id != NS_BL1U_IMAGE_ID) 269 panic(); 270 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 271 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 272 NS_BL1U_SIZE); 273 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 274 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 275 /* Initialize the GIC driver, cpu and distributor interfaces */ 276 gicv2_driver_init(&hikey960_gic_data); 277 gicv2_distif_init(); 278 gicv2_pcpu_distif_init(); 279 gicv2_cpuif_enable(); 280 /* CNTFRQ is read-only in EL1 */ 281 write_cntfrq_el0(plat_get_syscnt_freq2()); 282 data = read_cpacr_el1(); 283 do { 284 data |= 3 << 20; 285 write_cpacr_el1(data); 286 data = read_cpacr_el1(); 287 } while ((data & (3 << 20)) != (3 << 20)); 288 INFO("cpacr_el1:0x%x\n", data); 289 290 ep_info->args.arg0 = 0xffff & read_mpidr(); 291 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 292 DISABLE_ALL_EXCEPTIONS); 293 } 294