1*28b02e23SHaojian Zhuang /* 2*28b02e23SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*28b02e23SHaojian Zhuang * 4*28b02e23SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5*28b02e23SHaojian Zhuang */ 6*28b02e23SHaojian Zhuang 7*28b02e23SHaojian Zhuang #ifndef __HISI_PWRC_H__ 8*28b02e23SHaojian Zhuang #define __HISI_PWRC_H__ 9*28b02e23SHaojian Zhuang 10*28b02e23SHaojian Zhuang #include <hi3660.h> 11*28b02e23SHaojian Zhuang #include <hi3660_crg.h> 12*28b02e23SHaojian Zhuang 13*28b02e23SHaojian Zhuang #define PCTRL_BASE (PCTRL_REG_BASE) 14*28b02e23SHaojian Zhuang #define CRG_BASE (CRG_REG_BASE) 15*28b02e23SHaojian Zhuang 16*28b02e23SHaojian Zhuang #define SOC_CRGPERIPH_A53_PDCEN_ADDR(base) ((base) + (0x260)) 17*28b02e23SHaojian Zhuang #define SOC_CRGPERIPH_MAIA_PDCEN_ADDR(base) ((base) + (0x300)) 18*28b02e23SHaojian Zhuang 19*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE0_LOCK_ADDR(base) ((base) + (0x400)) 20*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE0_UNLOCK_ADDR(base) ((base) + (0x404)) 21*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE0_LOCK_ST_ADDR(base) ((base) + (0x408)) 22*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE1_LOCK_ADDR(base) ((base) + (0x40C)) 23*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE1_UNLOCK_ADDR(base) ((base) + (0x410)) 24*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE1_LOCK_ST_ADDR(base) ((base) + (0x414)) 25*28b02e23SHaojian Zhuang #define SOC_PCTRL_RESOURCE2_LOCK_ADDR(base) ((base) + (0x418)) 26*28b02e23SHaojian Zhuang 27*28b02e23SHaojian Zhuang #define SOC_SCTRL_SCBAKDATA3_ADDR(base) ((base) + (0x418)) 28*28b02e23SHaojian Zhuang #define SOC_SCTRL_SCBAKDATA8_ADDR(base) ((base) + (0x42C)) 29*28b02e23SHaojian Zhuang #define SOC_SCTRL_SCBAKDATA9_ADDR(base) ((base) + (0x430)) 30*28b02e23SHaojian Zhuang 31*28b02e23SHaojian Zhuang #define SOC_ACPU_SCTRL_BASE_ADDR (0xFFF0A000) 32*28b02e23SHaojian Zhuang 33*28b02e23SHaojian Zhuang void hisi_cpuidle_lock(unsigned int cluster, unsigned int core); 34*28b02e23SHaojian Zhuang void hisi_cpuidle_unlock(unsigned int cluster, unsigned int core); 35*28b02e23SHaojian Zhuang void hisi_set_cpuidle_flag(unsigned int cluster, unsigned int core); 36*28b02e23SHaojian Zhuang void hisi_clear_cpuidle_flag(unsigned int cluster, unsigned int core); 37*28b02e23SHaojian Zhuang void hisi_set_cpu_boot_flag(unsigned int cluster, unsigned int core); 38*28b02e23SHaojian Zhuang void hisi_clear_cpu_boot_flag(unsigned int cluster, unsigned int core); 39*28b02e23SHaojian Zhuang int cluster_is_powered_on(unsigned int cluster); 40*28b02e23SHaojian Zhuang void hisi_enter_core_idle(unsigned int cluster, unsigned int core); 41*28b02e23SHaojian Zhuang void hisi_enter_cluster_idle(unsigned int cluster, unsigned int core); 42*28b02e23SHaojian Zhuang int hisi_test_ap_suspend_flag(unsigned int cluster); 43*28b02e23SHaojian Zhuang void hisi_enter_ap_suspend(unsigned int cluster, unsigned int core); 44*28b02e23SHaojian Zhuang 45*28b02e23SHaojian Zhuang 46*28b02e23SHaojian Zhuang /* pdc api */ 47*28b02e23SHaojian Zhuang void hisi_pdc_mask_cluster_wakeirq(unsigned int cluster); 48*28b02e23SHaojian Zhuang int hisi_test_pwrdn_allcores(unsigned int cluster, unsigned int core); 49*28b02e23SHaojian Zhuang void hisi_disable_pdc(unsigned int cluster); 50*28b02e23SHaojian Zhuang void hisi_enable_pdc(unsigned int cluster); 51*28b02e23SHaojian Zhuang void hisi_powerup_core(unsigned int cluster, unsigned int core); 52*28b02e23SHaojian Zhuang void hisi_powerdn_core(unsigned int cluster, unsigned int core); 53*28b02e23SHaojian Zhuang void hisi_powerup_cluster(unsigned int cluster, unsigned int core); 54*28b02e23SHaojian Zhuang void hisi_powerdn_cluster(unsigned int cluster, unsigned int core); 55*28b02e23SHaojian Zhuang unsigned int hisi_test_cpu_down(unsigned int cluster, unsigned int core); 56*28b02e23SHaojian Zhuang 57*28b02e23SHaojian Zhuang #endif /* __HISI_PWRC_H__ */ 58