xref: /rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S (revision 2f2abcf4ba37bdd1332111c240961aae509c5d9c)
1*2f2abcf4SHaojian Zhuang/*
2*2f2abcf4SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3*2f2abcf4SHaojian Zhuang *
4*2f2abcf4SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause
5*2f2abcf4SHaojian Zhuang */
6*2f2abcf4SHaojian Zhuang
7*2f2abcf4SHaojian Zhuang#include <arch.h>
8*2f2abcf4SHaojian Zhuang#include <asm_macros.S>
9*2f2abcf4SHaojian Zhuang#include "../hikey960_def.h"
10*2f2abcf4SHaojian Zhuang
11*2f2abcf4SHaojian Zhuang	.globl	plat_my_core_pos
12*2f2abcf4SHaojian Zhuang	.globl	platform_mem_init
13*2f2abcf4SHaojian Zhuang	.globl	plat_crash_console_init
14*2f2abcf4SHaojian Zhuang	.globl	plat_crash_console_putc
15*2f2abcf4SHaojian Zhuang	.globl	plat_report_exception
16*2f2abcf4SHaojian Zhuang	.globl	plat_reset_handler
17*2f2abcf4SHaojian Zhuang
18*2f2abcf4SHaojian Zhuangfunc plat_my_core_pos
19*2f2abcf4SHaojian Zhuang	mrs	x0, mpidr_el1
20*2f2abcf4SHaojian Zhuang	and	x1, x0, #MPIDR_CPU_MASK
21*2f2abcf4SHaojian Zhuang	and	x0, x0, #MPIDR_CLUSTER_MASK
22*2f2abcf4SHaojian Zhuang	add	x0, x1, x0, LSR #6
23*2f2abcf4SHaojian Zhuang	ret
24*2f2abcf4SHaojian Zhuangendfunc plat_my_core_pos
25*2f2abcf4SHaojian Zhuang
26*2f2abcf4SHaojian Zhuang	/* -----------------------------------------------------
27*2f2abcf4SHaojian Zhuang	 * void platform_mem_init(void);
28*2f2abcf4SHaojian Zhuang	 *
29*2f2abcf4SHaojian Zhuang	 * We don't need to carry out any memory initialization
30*2f2abcf4SHaojian Zhuang	 * on HIKEY. The Secure RAM is accessible straight away.
31*2f2abcf4SHaojian Zhuang	 * -----------------------------------------------------
32*2f2abcf4SHaojian Zhuang	 */
33*2f2abcf4SHaojian Zhuangfunc platform_mem_init
34*2f2abcf4SHaojian Zhuang	ret
35*2f2abcf4SHaojian Zhuangendfunc platform_mem_init
36*2f2abcf4SHaojian Zhuang
37*2f2abcf4SHaojian Zhuang	/* ---------------------------------------------
38*2f2abcf4SHaojian Zhuang	 * int plat_crash_console_init(void)
39*2f2abcf4SHaojian Zhuang	 * Function to initialize the crash console
40*2f2abcf4SHaojian Zhuang	 * without a C Runtime to print crash report.
41*2f2abcf4SHaojian Zhuang	 * Clobber list : x0, x1, x2
42*2f2abcf4SHaojian Zhuang	 * ---------------------------------------------
43*2f2abcf4SHaojian Zhuang	 */
44*2f2abcf4SHaojian Zhuangfunc plat_crash_console_init
45*2f2abcf4SHaojian Zhuang	mov_imm	x0, CRASH_CONSOLE_BASE
46*2f2abcf4SHaojian Zhuang	mov_imm	x1, PL011_UART_CLK_IN_HZ
47*2f2abcf4SHaojian Zhuang	mov_imm	x2, PL011_BAUDRATE
48*2f2abcf4SHaojian Zhuang	b	console_core_init
49*2f2abcf4SHaojian Zhuangendfunc plat_crash_console_init
50*2f2abcf4SHaojian Zhuang
51*2f2abcf4SHaojian Zhuang	/* ---------------------------------------------
52*2f2abcf4SHaojian Zhuang	 * int plat_crash_console_putc(int c)
53*2f2abcf4SHaojian Zhuang	 * Function to print a character on the crash
54*2f2abcf4SHaojian Zhuang	 * console without a C Runtime.
55*2f2abcf4SHaojian Zhuang	 * Clobber list : x1, x2
56*2f2abcf4SHaojian Zhuang	 * ---------------------------------------------
57*2f2abcf4SHaojian Zhuang	 */
58*2f2abcf4SHaojian Zhuangfunc plat_crash_console_putc
59*2f2abcf4SHaojian Zhuang	mov_imm	x1, CRASH_CONSOLE_BASE
60*2f2abcf4SHaojian Zhuang	b	console_core_putc
61*2f2abcf4SHaojian Zhuangendfunc plat_crash_console_putc
62*2f2abcf4SHaojian Zhuang
63*2f2abcf4SHaojian Zhuang	/* ---------------------------------------------
64*2f2abcf4SHaojian Zhuang	 * void plat_report_exception(unsigned int type)
65*2f2abcf4SHaojian Zhuang	 * Function to report an unhandled exception
66*2f2abcf4SHaojian Zhuang	 * with platform-specific means.
67*2f2abcf4SHaojian Zhuang	 * On HIKEY platform, it updates the LEDs
68*2f2abcf4SHaojian Zhuang	 * to indicate where we are
69*2f2abcf4SHaojian Zhuang	 * ---------------------------------------------
70*2f2abcf4SHaojian Zhuang	 */
71*2f2abcf4SHaojian Zhuangfunc plat_report_exception
72*2f2abcf4SHaojian Zhuang	mov	x8, x30
73*2f2abcf4SHaojian Zhuang
74*2f2abcf4SHaojian Zhuang	/* Turn on LED according to x0 (0 -- f) */
75*2f2abcf4SHaojian Zhuang	ldr	x2, =0xf7020000
76*2f2abcf4SHaojian Zhuang	and	x1, x0, #1
77*2f2abcf4SHaojian Zhuang	str	w1, [x2, #4]
78*2f2abcf4SHaojian Zhuang	and	x1, x0, #2
79*2f2abcf4SHaojian Zhuang	str	w1, [x2, #8]
80*2f2abcf4SHaojian Zhuang	and	x1, x0, #4
81*2f2abcf4SHaojian Zhuang	str	w1, [x2, #16]
82*2f2abcf4SHaojian Zhuang	and	x1, x0, #8
83*2f2abcf4SHaojian Zhuang	str	w1, [x2, #32]
84*2f2abcf4SHaojian Zhuang
85*2f2abcf4SHaojian Zhuang	mrs	x2, currentel
86*2f2abcf4SHaojian Zhuang	and	x2, x2, #0x0c
87*2f2abcf4SHaojian Zhuang	/* Check EL1 */
88*2f2abcf4SHaojian Zhuang	cmp	x2, #0x04
89*2f2abcf4SHaojian Zhuang	beq	plat_report_el1
90*2f2abcf4SHaojian Zhuang
91*2f2abcf4SHaojian Zhuang	adr	x4, plat_err_str
92*2f2abcf4SHaojian Zhuang	bl	asm_print_str
93*2f2abcf4SHaojian Zhuang
94*2f2abcf4SHaojian Zhuang	adr	x4, esr_el3_str
95*2f2abcf4SHaojian Zhuang	bl	asm_print_str
96*2f2abcf4SHaojian Zhuang
97*2f2abcf4SHaojian Zhuang	mrs	x4, esr_el3
98*2f2abcf4SHaojian Zhuang	bl	asm_print_hex
99*2f2abcf4SHaojian Zhuang
100*2f2abcf4SHaojian Zhuang	adr	x4, elr_el3_str
101*2f2abcf4SHaojian Zhuang	bl	asm_print_str
102*2f2abcf4SHaojian Zhuang
103*2f2abcf4SHaojian Zhuang	mrs	x4, elr_el3
104*2f2abcf4SHaojian Zhuang	bl	asm_print_hex
105*2f2abcf4SHaojian Zhuang	b	plat_report_end
106*2f2abcf4SHaojian Zhuang
107*2f2abcf4SHaojian Zhuangplat_report_el1:
108*2f2abcf4SHaojian Zhuang	adr	x4, plat_err_str
109*2f2abcf4SHaojian Zhuang	bl	asm_print_str
110*2f2abcf4SHaojian Zhuang
111*2f2abcf4SHaojian Zhuang	adr	x4, esr_el1_str
112*2f2abcf4SHaojian Zhuang	bl	asm_print_str
113*2f2abcf4SHaojian Zhuang
114*2f2abcf4SHaojian Zhuang	mrs	x4, esr_el1
115*2f2abcf4SHaojian Zhuang	bl	asm_print_hex
116*2f2abcf4SHaojian Zhuang
117*2f2abcf4SHaojian Zhuang	adr	x4, elr_el1_str
118*2f2abcf4SHaojian Zhuang	bl	asm_print_str
119*2f2abcf4SHaojian Zhuang
120*2f2abcf4SHaojian Zhuang	mrs	x4, elr_el1
121*2f2abcf4SHaojian Zhuang	bl	asm_print_hex
122*2f2abcf4SHaojian Zhuangplat_report_end:
123*2f2abcf4SHaojian Zhuang	mov	x30, x8
124*2f2abcf4SHaojian Zhuang	ret
125*2f2abcf4SHaojian Zhuangendfunc plat_report_exception
126*2f2abcf4SHaojian Zhuang
127*2f2abcf4SHaojian Zhuang	/* -----------------------------------------------------
128*2f2abcf4SHaojian Zhuang	 * void plat_reset_handler(void);
129*2f2abcf4SHaojian Zhuang	 * -----------------------------------------------------
130*2f2abcf4SHaojian Zhuang	 */
131*2f2abcf4SHaojian Zhuangfunc plat_reset_handler
132*2f2abcf4SHaojian Zhuang	ret
133*2f2abcf4SHaojian Zhuangendfunc plat_reset_handler
134*2f2abcf4SHaojian Zhuang
135*2f2abcf4SHaojian Zhuang.section .rodata.rev_err_str, "aS"
136*2f2abcf4SHaojian Zhuangplat_err_str:
137*2f2abcf4SHaojian Zhuang	.asciz "\nPlatform exception reporting:"
138*2f2abcf4SHaojian Zhuangesr_el3_str:
139*2f2abcf4SHaojian Zhuang	.asciz "\nESR_EL3: "
140*2f2abcf4SHaojian Zhuangelr_el3_str:
141*2f2abcf4SHaojian Zhuang	.asciz "\nELR_EL3: "
142*2f2abcf4SHaojian Zhuangesr_el1_str:
143*2f2abcf4SHaojian Zhuang	.asciz "\nESR_EL1: "
144*2f2abcf4SHaojian Zhuangelr_el1_str:
145*2f2abcf4SHaojian Zhuang	.asciz "\nELR_EL1: "
146