xref: /rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/hikey960_common.c (revision e8a87acd4b7f3c526de036920df42230e37e6144)
12f2abcf4SHaojian Zhuang /*
22f2abcf4SHaojian Zhuang  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
32f2abcf4SHaojian Zhuang  *
42f2abcf4SHaojian Zhuang  * SPDX-License-Identifier: BSD-3-Clause
52f2abcf4SHaojian Zhuang  */
62f2abcf4SHaojian Zhuang 
72f2abcf4SHaojian Zhuang #include <arch_helpers.h>
82f2abcf4SHaojian Zhuang #include <arm_gic.h>
92f2abcf4SHaojian Zhuang #include <assert.h>
102f2abcf4SHaojian Zhuang #include <bl_common.h>
112f2abcf4SHaojian Zhuang #include <debug.h>
122f2abcf4SHaojian Zhuang #include <mmio.h>
132f2abcf4SHaojian Zhuang #include <platform.h>
142f2abcf4SHaojian Zhuang #include <platform_def.h>
152f2abcf4SHaojian Zhuang #include <xlat_tables.h>
162f2abcf4SHaojian Zhuang 
172f2abcf4SHaojian Zhuang #include "../hikey960_def.h"
182f2abcf4SHaojian Zhuang #include "../hikey960_private.h"
192f2abcf4SHaojian Zhuang 
202f2abcf4SHaojian Zhuang #define MAP_DDR		MAP_REGION_FLAT(DDR_BASE,			\
212f2abcf4SHaojian Zhuang 					DDR_SIZE,			\
222f2abcf4SHaojian Zhuang 					MT_MEMORY | MT_RW | MT_NS)
232f2abcf4SHaojian Zhuang 
242f2abcf4SHaojian Zhuang #define MAP_DEVICE	MAP_REGION_FLAT(DEVICE_BASE,			\
252f2abcf4SHaojian Zhuang 					DEVICE_SIZE,			\
262f2abcf4SHaojian Zhuang 					MT_DEVICE | MT_RW | MT_SECURE)
272f2abcf4SHaojian Zhuang 
282f2abcf4SHaojian Zhuang #define MAP_BL1_RW	MAP_REGION_FLAT(BL1_RW_BASE,			\
292f2abcf4SHaojian Zhuang 					BL1_RW_LIMIT - BL1_RW_BASE,	\
302f2abcf4SHaojian Zhuang 					MT_MEMORY | MT_RW | MT_NS)
312f2abcf4SHaojian Zhuang 
322f2abcf4SHaojian Zhuang #define MAP_UFS_DATA	MAP_REGION_FLAT(HIKEY960_UFS_DATA_BASE,		\
332f2abcf4SHaojian Zhuang 					HIKEY960_UFS_DATA_SIZE,		\
342f2abcf4SHaojian Zhuang 					MT_MEMORY | MT_RW | MT_NS)
352f2abcf4SHaojian Zhuang 
362f2abcf4SHaojian Zhuang #define MAP_UFS_DESC	MAP_REGION_FLAT(HIKEY960_UFS_DESC_BASE,		\
372f2abcf4SHaojian Zhuang 					HIKEY960_UFS_DESC_SIZE,		\
382f2abcf4SHaojian Zhuang 					MT_MEMORY | MT_RW | MT_NS)
392f2abcf4SHaojian Zhuang 
405e3325e7SVictor Chong #define MAP_TSP_MEM	MAP_REGION_FLAT(TSP_SEC_MEM_BASE,		\
415e3325e7SVictor Chong 					TSP_SEC_MEM_SIZE,		\
425e3325e7SVictor Chong 					MT_MEMORY | MT_RW | MT_SECURE)
435e3325e7SVictor Chong 
44b16bb16eSVictor Chong #if LOAD_IMAGE_V2
45b16bb16eSVictor Chong #ifdef SPD_opteed
46b16bb16eSVictor Chong #define MAP_OPTEE_PAGEABLE	MAP_REGION_FLAT(		\
47b16bb16eSVictor Chong 					HIKEY960_OPTEE_PAGEABLE_LOAD_BASE,	\
48b16bb16eSVictor Chong 					HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE,	\
49b16bb16eSVictor Chong 					MT_MEMORY | MT_RW | MT_SECURE)
50b16bb16eSVictor Chong #endif
51b16bb16eSVictor Chong #endif
52b16bb16eSVictor Chong 
532f2abcf4SHaojian Zhuang /*
542f2abcf4SHaojian Zhuang  * Table of regions for different BL stages to map using the MMU.
552f2abcf4SHaojian Zhuang  * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
562f2abcf4SHaojian Zhuang  * hikey960_init_mmu_elx() will give the available subset of that,
572f2abcf4SHaojian Zhuang  */
58*e8a87acdSRoberto Vargas #ifdef IMAGE_BL1
592f2abcf4SHaojian Zhuang static const mmap_region_t hikey960_mmap[] = {
602f2abcf4SHaojian Zhuang 	MAP_UFS_DATA,
612f2abcf4SHaojian Zhuang 	MAP_BL1_RW,
622f2abcf4SHaojian Zhuang 	MAP_UFS_DESC,
632f2abcf4SHaojian Zhuang 	MAP_DEVICE,
642f2abcf4SHaojian Zhuang 	{0}
652f2abcf4SHaojian Zhuang };
662f2abcf4SHaojian Zhuang #endif
672f2abcf4SHaojian Zhuang 
68*e8a87acdSRoberto Vargas #ifdef IMAGE_BL2
692f2abcf4SHaojian Zhuang static const mmap_region_t hikey960_mmap[] = {
702f2abcf4SHaojian Zhuang 	MAP_DDR,
712f2abcf4SHaojian Zhuang 	MAP_DEVICE,
725e3325e7SVictor Chong 	MAP_TSP_MEM,
73b16bb16eSVictor Chong #if LOAD_IMAGE_V2
74b16bb16eSVictor Chong #ifdef SPD_opteed
75b16bb16eSVictor Chong 	MAP_OPTEE_PAGEABLE,
76b16bb16eSVictor Chong #endif
77b16bb16eSVictor Chong #endif
782f2abcf4SHaojian Zhuang 	{0}
792f2abcf4SHaojian Zhuang };
802f2abcf4SHaojian Zhuang #endif
812f2abcf4SHaojian Zhuang 
82*e8a87acdSRoberto Vargas #ifdef IMAGE_BL31
832f2abcf4SHaojian Zhuang static const mmap_region_t hikey960_mmap[] = {
842f2abcf4SHaojian Zhuang 	MAP_DEVICE,
855e3325e7SVictor Chong 	MAP_TSP_MEM,
865e3325e7SVictor Chong 	{0}
875e3325e7SVictor Chong };
885e3325e7SVictor Chong #endif
895e3325e7SVictor Chong 
90*e8a87acdSRoberto Vargas #ifdef IMAGE_BL32
915e3325e7SVictor Chong static const mmap_region_t hikey960_mmap[] = {
925e3325e7SVictor Chong 	MAP_DEVICE,
935e3325e7SVictor Chong 	MAP_DDR,
942f2abcf4SHaojian Zhuang 	{0}
952f2abcf4SHaojian Zhuang };
962f2abcf4SHaojian Zhuang #endif
972f2abcf4SHaojian Zhuang 
982f2abcf4SHaojian Zhuang /*
992f2abcf4SHaojian Zhuang  * Macro generating the code for the function setting up the pagetables as per
1002f2abcf4SHaojian Zhuang  * the platform memory map & initialize the mmu, for the given exception level
1012f2abcf4SHaojian Zhuang  */
1022f2abcf4SHaojian Zhuang #define HIKEY960_CONFIGURE_MMU_EL(_el)					\
1032f2abcf4SHaojian Zhuang 	void hikey960_init_mmu_el##_el(unsigned long total_base,	\
1042f2abcf4SHaojian Zhuang 				unsigned long total_size,		\
1052f2abcf4SHaojian Zhuang 				unsigned long ro_start,			\
1062f2abcf4SHaojian Zhuang 				unsigned long ro_limit,			\
1072f2abcf4SHaojian Zhuang 				unsigned long coh_start,		\
1082f2abcf4SHaojian Zhuang 				unsigned long coh_limit)		\
1092f2abcf4SHaojian Zhuang 	{								\
1102f2abcf4SHaojian Zhuang 	       mmap_add_region(total_base, total_base,			\
1112f2abcf4SHaojian Zhuang 			       total_size,				\
1122f2abcf4SHaojian Zhuang 			       MT_MEMORY | MT_RW | MT_SECURE);		\
1132f2abcf4SHaojian Zhuang 	       mmap_add_region(ro_start, ro_start,			\
1142f2abcf4SHaojian Zhuang 			       ro_limit - ro_start,			\
1152f2abcf4SHaojian Zhuang 			       MT_MEMORY | MT_RO | MT_SECURE);		\
1162f2abcf4SHaojian Zhuang 	       mmap_add_region(coh_start, coh_start,			\
1172f2abcf4SHaojian Zhuang 			       coh_limit - coh_start,			\
1182f2abcf4SHaojian Zhuang 			       MT_DEVICE | MT_RW | MT_SECURE);		\
1192f2abcf4SHaojian Zhuang 	       mmap_add(hikey960_mmap);					\
1202f2abcf4SHaojian Zhuang 	       init_xlat_tables();					\
1212f2abcf4SHaojian Zhuang 									\
1222f2abcf4SHaojian Zhuang 	       enable_mmu_el##_el(0);					\
1232f2abcf4SHaojian Zhuang 	}
1242f2abcf4SHaojian Zhuang 
1252f2abcf4SHaojian Zhuang /* Define EL1 and EL3 variants of the function initialising the MMU */
1262f2abcf4SHaojian Zhuang HIKEY960_CONFIGURE_MMU_EL(1)
1272f2abcf4SHaojian Zhuang HIKEY960_CONFIGURE_MMU_EL(3)
1282f2abcf4SHaojian Zhuang 
1292f2abcf4SHaojian Zhuang unsigned long plat_get_ns_image_entrypoint(void)
1302f2abcf4SHaojian Zhuang {
1312f2abcf4SHaojian Zhuang 	return NS_BL1U_BASE;
1322f2abcf4SHaojian Zhuang }
1332f2abcf4SHaojian Zhuang 
1342f2abcf4SHaojian Zhuang unsigned int plat_get_syscnt_freq2(void)
1352f2abcf4SHaojian Zhuang {
1362f2abcf4SHaojian Zhuang 	return 1920000;
1372f2abcf4SHaojian Zhuang }
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