12f2abcf4SHaojian Zhuang /* 2*8495c03aSHaojian Zhuang * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 32f2abcf4SHaojian Zhuang * 42f2abcf4SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 52f2abcf4SHaojian Zhuang */ 62f2abcf4SHaojian Zhuang 72f2abcf4SHaojian Zhuang #include <arch_helpers.h> 82f2abcf4SHaojian Zhuang #include <arm_gic.h> 92f2abcf4SHaojian Zhuang #include <assert.h> 102f2abcf4SHaojian Zhuang #include <bl_common.h> 112f2abcf4SHaojian Zhuang #include <debug.h> 122f2abcf4SHaojian Zhuang #include <mmio.h> 132f2abcf4SHaojian Zhuang #include <platform.h> 142f2abcf4SHaojian Zhuang #include <platform_def.h> 152f2abcf4SHaojian Zhuang #include <xlat_tables.h> 162f2abcf4SHaojian Zhuang 172f2abcf4SHaojian Zhuang #include "../hikey960_def.h" 182f2abcf4SHaojian Zhuang #include "../hikey960_private.h" 192f2abcf4SHaojian Zhuang 202f2abcf4SHaojian Zhuang #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ 21*8495c03aSHaojian Zhuang DDR_SIZE - DDR_SEC_SIZE, \ 222f2abcf4SHaojian Zhuang MT_MEMORY | MT_RW | MT_NS) 232f2abcf4SHaojian Zhuang 242f2abcf4SHaojian Zhuang #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \ 252f2abcf4SHaojian Zhuang DEVICE_SIZE, \ 262f2abcf4SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 272f2abcf4SHaojian Zhuang 282f2abcf4SHaojian Zhuang #define MAP_BL1_RW MAP_REGION_FLAT(BL1_RW_BASE, \ 292f2abcf4SHaojian Zhuang BL1_RW_LIMIT - BL1_RW_BASE, \ 302f2abcf4SHaojian Zhuang MT_MEMORY | MT_RW | MT_NS) 312f2abcf4SHaojian Zhuang 322f2abcf4SHaojian Zhuang #define MAP_UFS_DATA MAP_REGION_FLAT(HIKEY960_UFS_DATA_BASE, \ 332f2abcf4SHaojian Zhuang HIKEY960_UFS_DATA_SIZE, \ 342f2abcf4SHaojian Zhuang MT_MEMORY | MT_RW | MT_NS) 352f2abcf4SHaojian Zhuang 362f2abcf4SHaojian Zhuang #define MAP_UFS_DESC MAP_REGION_FLAT(HIKEY960_UFS_DESC_BASE, \ 372f2abcf4SHaojian Zhuang HIKEY960_UFS_DESC_SIZE, \ 382f2abcf4SHaojian Zhuang MT_MEMORY | MT_RW | MT_NS) 392f2abcf4SHaojian Zhuang 405e3325e7SVictor Chong #define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ 415e3325e7SVictor Chong TSP_SEC_MEM_SIZE, \ 425e3325e7SVictor Chong MT_MEMORY | MT_RW | MT_SECURE) 435e3325e7SVictor Chong 442f2abcf4SHaojian Zhuang /* 452f2abcf4SHaojian Zhuang * Table of regions for different BL stages to map using the MMU. 462f2abcf4SHaojian Zhuang * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 472f2abcf4SHaojian Zhuang * hikey960_init_mmu_elx() will give the available subset of that, 482f2abcf4SHaojian Zhuang */ 49e8a87acdSRoberto Vargas #ifdef IMAGE_BL1 502f2abcf4SHaojian Zhuang static const mmap_region_t hikey960_mmap[] = { 512f2abcf4SHaojian Zhuang MAP_UFS_DATA, 522f2abcf4SHaojian Zhuang MAP_BL1_RW, 532f2abcf4SHaojian Zhuang MAP_UFS_DESC, 542f2abcf4SHaojian Zhuang MAP_DEVICE, 552f2abcf4SHaojian Zhuang {0} 562f2abcf4SHaojian Zhuang }; 572f2abcf4SHaojian Zhuang #endif 582f2abcf4SHaojian Zhuang 59e8a87acdSRoberto Vargas #ifdef IMAGE_BL2 602f2abcf4SHaojian Zhuang static const mmap_region_t hikey960_mmap[] = { 612f2abcf4SHaojian Zhuang MAP_DDR, 622f2abcf4SHaojian Zhuang MAP_DEVICE, 635e3325e7SVictor Chong MAP_TSP_MEM, 642f2abcf4SHaojian Zhuang {0} 652f2abcf4SHaojian Zhuang }; 662f2abcf4SHaojian Zhuang #endif 672f2abcf4SHaojian Zhuang 68e8a87acdSRoberto Vargas #ifdef IMAGE_BL31 692f2abcf4SHaojian Zhuang static const mmap_region_t hikey960_mmap[] = { 702f2abcf4SHaojian Zhuang MAP_DEVICE, 715e3325e7SVictor Chong MAP_TSP_MEM, 725e3325e7SVictor Chong {0} 735e3325e7SVictor Chong }; 745e3325e7SVictor Chong #endif 755e3325e7SVictor Chong 76e8a87acdSRoberto Vargas #ifdef IMAGE_BL32 775e3325e7SVictor Chong static const mmap_region_t hikey960_mmap[] = { 785e3325e7SVictor Chong MAP_DEVICE, 795e3325e7SVictor Chong MAP_DDR, 802f2abcf4SHaojian Zhuang {0} 812f2abcf4SHaojian Zhuang }; 822f2abcf4SHaojian Zhuang #endif 832f2abcf4SHaojian Zhuang 842f2abcf4SHaojian Zhuang /* 852f2abcf4SHaojian Zhuang * Macro generating the code for the function setting up the pagetables as per 862f2abcf4SHaojian Zhuang * the platform memory map & initialize the mmu, for the given exception level 872f2abcf4SHaojian Zhuang */ 882f2abcf4SHaojian Zhuang #define HIKEY960_CONFIGURE_MMU_EL(_el) \ 892f2abcf4SHaojian Zhuang void hikey960_init_mmu_el##_el(unsigned long total_base, \ 902f2abcf4SHaojian Zhuang unsigned long total_size, \ 912f2abcf4SHaojian Zhuang unsigned long ro_start, \ 922f2abcf4SHaojian Zhuang unsigned long ro_limit, \ 932f2abcf4SHaojian Zhuang unsigned long coh_start, \ 942f2abcf4SHaojian Zhuang unsigned long coh_limit) \ 952f2abcf4SHaojian Zhuang { \ 962f2abcf4SHaojian Zhuang mmap_add_region(total_base, total_base, \ 972f2abcf4SHaojian Zhuang total_size, \ 982f2abcf4SHaojian Zhuang MT_MEMORY | MT_RW | MT_SECURE); \ 992f2abcf4SHaojian Zhuang mmap_add_region(ro_start, ro_start, \ 1002f2abcf4SHaojian Zhuang ro_limit - ro_start, \ 1012f2abcf4SHaojian Zhuang MT_MEMORY | MT_RO | MT_SECURE); \ 1022f2abcf4SHaojian Zhuang mmap_add_region(coh_start, coh_start, \ 1032f2abcf4SHaojian Zhuang coh_limit - coh_start, \ 1042f2abcf4SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE); \ 1052f2abcf4SHaojian Zhuang mmap_add(hikey960_mmap); \ 1062f2abcf4SHaojian Zhuang init_xlat_tables(); \ 1072f2abcf4SHaojian Zhuang \ 1082f2abcf4SHaojian Zhuang enable_mmu_el##_el(0); \ 1092f2abcf4SHaojian Zhuang } 1102f2abcf4SHaojian Zhuang 1112f2abcf4SHaojian Zhuang /* Define EL1 and EL3 variants of the function initialising the MMU */ 1122f2abcf4SHaojian Zhuang HIKEY960_CONFIGURE_MMU_EL(1) 1132f2abcf4SHaojian Zhuang HIKEY960_CONFIGURE_MMU_EL(3) 1142f2abcf4SHaojian Zhuang 1152f2abcf4SHaojian Zhuang unsigned long plat_get_ns_image_entrypoint(void) 1162f2abcf4SHaojian Zhuang { 1172f2abcf4SHaojian Zhuang return NS_BL1U_BASE; 1182f2abcf4SHaojian Zhuang } 1192f2abcf4SHaojian Zhuang 1202f2abcf4SHaojian Zhuang unsigned int plat_get_syscnt_freq2(void) 1212f2abcf4SHaojian Zhuang { 1222f2abcf4SHaojian Zhuang return 1920000; 1232f2abcf4SHaojian Zhuang } 124